Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60381 )
Change subject: ec/chromeec/ec/acpi: Use Printf() for debug prints
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/60381/comment/d90090c3_d17e0416
PS4, Line 9: and coreboot.rom remains identical
> Sorry, forgot to add that. I wrote the commit message first and tested it later. […]
Done
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62825 )
Change subject: soc/intel/elkhartlake: Enable SPI flash caching before payload is loaded
......................................................................
soc/intel/elkhartlake: Enable SPI flash caching before payload is loaded
This patch enables SPI flash caching temporary before the payload is
loaded. This speeds up payload loading and measuring a lot on Elkhart
Lake.
Change-Id: I37e554b5c32dca00e74af6af4a93ed2c07d71c5f
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/elkhartlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/62825/1
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index a1f7794..362c24b 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -26,6 +26,7 @@
select INTEL_DESCRIPTOR_MODE_CAPABLE
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
+ select SOC_INTEL_ENABLE_FLASH_CACHING
select MP_SERVICES_PPI_V1
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
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Zhuohao Lee has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 )
Change subject: mb/google/brask/variants/moli: init overridetree for moli
......................................................................
Patch Set 26:
(1 comment)
File src/mainboard/google/brya/variants/moli/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62321/comment/6e7e774f_db3f83f8
PS26, Line 2: 4 6
Should be 4 5? From the b/215806030, you only allocate 2 bit for the DB.
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62765 )
Change subject: Documentation/tutorial/part1.md: Add Fedora package `patch`
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62765/comment/d8006529_3b0afd61
PS2, Line 8:
> I imagine this is needed to build crossgcc. I'd mention so in the commit message: […]
Done
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Hello Wisley Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62823
to review the following change.
Change subject: ec/google/chromeec: Change loglevel prefix
......................................................................
ec/google/chromeec: Change loglevel prefix
In most boards, it doesn't write OEM_NAME in CBI to override the
manufacturer name of smbios.
It' better use the "BIOS_INFO" than "BIOS_ERR"
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I52eb1e6926eaac30b1dbee13ab750ef15b466d89
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
---
M src/ec/google/chromeec/ec_smbios.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62823/1
diff --git a/src/ec/google/chromeec/ec_smbios.c b/src/ec/google/chromeec/ec_smbios.c
index 1ee7283..d62a0a0 100644
--- a/src/ec/google/chromeec/ec_smbios.c
+++ b/src/ec/google/chromeec/ec_smbios.c
@@ -29,7 +29,7 @@
if (google_chromeec_cbi_get_oem_name(&oem_name[0],
ARRAY_SIZE(oem_name)) < 0) {
- printk(BIOS_ERR, "Couldn't obtain OEM name from CBI\n");
+ printk(BIOS_INFO, "Couldn't obtain OEM name from CBI\n");
manuf = CONFIG_MAINBOARD_SMBIOS_MANUFACTURER;
} else {
manuf = &oem_name[0];
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Hello Wisley Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/62822
to review the following change.
Change subject: driver/intel/usb4/retimer: Change loglevel prefix
......................................................................
driver/intel/usb4/retimer: Change loglevel prefix
In usb4_retimer_fill_ssdt(), it search all dpf ports and shows message
in not support dpf ports.
It's not error and changes the loglevel prefix to BIOS_INFO.
BUG=b:222038287
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com>
Change-Id: I508ec7662e078893f944edb3d68364c57d5c5a73
---
M src/drivers/intel/usb4/retimer/retimer.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/62822/1
diff --git a/src/drivers/intel/usb4/retimer/retimer.c b/src/drivers/intel/usb4/retimer/retimer.c
index 0c027eb..58ef2a8 100644
--- a/src/drivers/intel/usb4/retimer/retimer.c
+++ b/src/drivers/intel/usb4/retimer/retimer.c
@@ -358,7 +358,7 @@
for (dfp_port = 0; dfp_port < DFP_NUM_MAX; dfp_port++) {
if (!config->dfp[dfp_port].power_gpio.pin_count) {
- printk(BIOS_ERR, "%s: No DFP%1d power GPIO for %s\n",
+ printk(BIOS_INFO, "%s: No DFP%1d power GPIO for %s\n",
__func__, dfp_port, dev_path(dev));
continue;
}
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62808 )
Change subject: hp/z220_series: Convert z220_sff_workstation into variant
......................................................................
Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62808/comment/e844f291_8177e9b7
PS1, Line 7: hp/z220_series: Convert z220_sff_workstation into variant
mb/hp/z220_series: ...
https://review.coreboot.org/c/coreboot/+/62808/comment/519fb83b_d9472835
PS1, Line 11: $ diff static.c ~/static.c.orig
Please build with BUILD_TIMELESS=1 and with `INCLUDE_CONFIG_FILE` (General setup -> Include the coreboot .config file ...) disabled. Compare the coreboot.rom binary before and after this patch.
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