coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype
by Subrata Banik (Code Review) 15 Mar '22

15 Mar '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62736 ) Change subject: {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype ...................................................................... {mb, soc}: Change `memcfg_init()` and `variant_memory_init()` prototype This patch modifies `memcfg_init` and `variant_memory_init`functions argument from FSP_M_CONFIG to FSPM_UPD. This change in `memcfg_init()` argument will help to update the architectural FSP-M UPDs from common code blocks rather than going into SoC and/or mainboard implementation. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> --- M src/mainboard/google/brya/romstage.c M src/mainboard/google/deltaur/romstage.c M src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/deltaur/variants/deltan/memory.c M src/mainboard/google/deltaur/variants/deltaur/memory.c M src/mainboard/google/volteer/romstage.c M src/mainboard/intel/adlrvp/romstage_fsp_params.c M src/mainboard/intel/shadowmountain/romstage.c M src/mainboard/intel/tglrvp/romstage_fsp_params.c M src/mainboard/prodrive/atlas/romstage_fsp_params.c M src/mainboard/starlabs/labtop/variants/tgl/romstage.c M src/mainboard/system76/darp7/romstage.c M src/mainboard/system76/galp5/romstage.c M src/mainboard/system76/gaze16/romstage.c M src/mainboard/system76/lemp10/romstage.c M src/mainboard/system76/oryp8/romstage.c M src/soc/intel/alderlake/include/soc/meminit.h M src/soc/intel/alderlake/meminit.c M src/soc/intel/tigerlake/include/soc/meminit.h M src/soc/intel/tigerlake/meminit.c 20 files changed, 25 insertions(+), 30 deletions(-) Approvals: build bot (Jenkins): Verified Zhuohao Lee: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Tim Crawford: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/romstage.c b/src/mainboard/google/brya/romstage.c index a00cf32..2560840 100644 --- a/src/mainboard/google/brya/romstage.c +++ b/src/mainboard/google/brya/romstage.c @@ -9,7 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); bool half_populated = variant_is_half_populated(); struct mem_spd spd_info; @@ -21,7 +20,7 @@ const struct pad_config *pads; size_t pads_num; - memcfg_init(m_cfg, mem_config, &spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &spd_info, half_populated, &dimms_changed); if (dimms_changed) { memupd->FspmArchUpd.NvsBufferPtr = 0; memupd->FspmArchUpd.BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; diff --git a/src/mainboard/google/deltaur/romstage.c b/src/mainboard/google/deltaur/romstage.c index c04f6fb..f9d71a8 100644 --- a/src/mainboard/google/deltaur/romstage.c +++ b/src/mainboard/google/deltaur/romstage.c @@ -5,6 +5,5 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - variant_memory_init(mem_cfg); + variant_memory_init(mupd); } diff --git a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h index 7a4ed08..6804ef6 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/deltaur/variants/baseboard/include/baseboard/variants.h @@ -19,7 +19,7 @@ const struct cros_gpio *variant_cros_gpios(size_t *num); const struct mb_cfg *variant_memory_params(void); -void variant_memory_init(FSP_M_CONFIG *mem_cfg); +void variant_memory_init(FSPM_UPD *mupd); /* SKU ID structure */ typedef struct { diff --git a/src/mainboard/google/deltaur/variants/deltan/memory.c b/src/mainboard/google/deltaur/variants/deltan/memory.c index caa99a9..37c21cc 100644 --- a/src/mainboard/google/deltaur/variants/deltan/memory.c +++ b/src/mainboard/google/deltaur/variants/deltan/memory.c @@ -61,7 +61,7 @@ .ect = false, /* Disable Early Command Training */ }; -void variant_memory_init(FSP_M_CONFIG *mem_cfg) +void variant_memory_init(FSPM_UPD *mupd) { const struct mem_spd spd_info = { .topo = MEM_TOPO_DIMM_MODULE, @@ -77,5 +77,5 @@ new_board_cfg_ddr4.ddr4_config.dq_pins_interleaved = gpio_get(MEMORY_INTERLEAVED); - memcfg_init(mem_cfg, &new_board_cfg_ddr4, &spd_info, half_populated); + memcfg_init(mupd, &new_board_cfg_ddr4, &spd_info, half_populated); } diff --git a/src/mainboard/google/deltaur/variants/deltaur/memory.c b/src/mainboard/google/deltaur/variants/deltaur/memory.c index f8506df54..a2037a8 100644 --- a/src/mainboard/google/deltaur/variants/deltaur/memory.c +++ b/src/mainboard/google/deltaur/variants/deltaur/memory.c @@ -77,7 +77,7 @@ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); } -void variant_memory_init(FSP_M_CONFIG *mem_cfg) +void variant_memory_init(FSPM_UPD *mupd) { const struct mb_cfg *board_cfg = variant_memory_params(); const struct mem_spd spd_info = { @@ -85,5 +85,5 @@ .cbfs_index = variant_memory_sku(), }; const bool half_populated = false; - memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mupd, board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index 8cde5da..f9e507c 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -13,7 +13,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; const struct mb_cfg *board_cfg = variant_memory_params(); const struct mem_spd spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -21,7 +20,7 @@ }; bool half_populated = gpio_get(GPIO_MEM_CH_SEL); - memcfg_init(mem_cfg, board_cfg, &spd_info, half_populated); + memcfg_init(mupd, board_cfg, &spd_info, half_populated); memcfg_variant_init(mupd); } diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 5b5cc6b..8a24529 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -73,7 +73,7 @@ case ADL_P_DDR4_1: case ADL_P_DDR4_2: case ADL_P_DDR5_1: - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); break; case ADL_P_DDR5_2: @@ -84,7 +84,7 @@ case ADL_M_LP4: case ADL_M_LP5: case ADL_N_LP5: - memcfg_init(m_cfg, mem_config, &memory_down_spd_info, half_populated, + memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated, &dimms_changed); break; default: diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c index 0951936..eb08d18 100644 --- a/src/mainboard/intel/shadowmountain/romstage.c +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -9,7 +9,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = variant_memory_params(); const bool half_populated = false; bool dimms_changed = false; @@ -19,5 +18,5 @@ .cbfs_index = variant_memory_sku(), }; - memcfg_init(m_cfg, mem_config, &lp5_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 3341568..22859f6 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -40,8 +40,6 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { - FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; - const struct mb_cfg *mem_config = variant_memory_params(); const struct mem_spd spd_info = { .topo = MEM_TOPO_MEMORY_DOWN, @@ -49,6 +47,6 @@ }; bool half_populated = false; - memcfg_init(mem_cfg, mem_config, &spd_info, half_populated); + memcfg_init(mupd, mem_config, &spd_info, half_populated); } diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 9728a99..fae7100 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -29,7 +29,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - FSP_M_CONFIG *m_cfg = &memupd->FspmConfig; const struct mb_cfg *mem_config = &ddr5_mem_config; const bool half_populated = false; bool dimms_changed = false; @@ -48,5 +47,5 @@ }, }; - memcfg_init(m_cfg, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); + memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated, &dimms_changed); } diff --git a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c index 1d65c61..fed6efc 100644 --- a/src/mainboard/starlabs/labtop/variants/tgl/romstage.c +++ b/src/mainboard/starlabs/labtop/variants/tgl/romstage.c @@ -25,7 +25,7 @@ }, }; - memcfg_init(&mupd->FspmConfig, &mem_config, &ddr4_spd_info, half_populated); + memcfg_init(mupd, &mem_config, &ddr4_spd_info, half_populated); const uint8_t vtd = get_uint_option("vtd", 1); mupd->FspmConfig.VtdDisable = !vtd; diff --git a/src/mainboard/system76/darp7/romstage.c b/src/mainboard/system76/darp7/romstage.c index a72b647..eb4fd39 100644 --- a/src/mainboard/system76/darp7/romstage.c +++ b/src/mainboard/system76/darp7/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/galp5/romstage.c b/src/mainboard/system76/galp5/romstage.c index a72b647..eb4fd39 100644 --- a/src/mainboard/system76/galp5/romstage.c +++ b/src/mainboard/system76/galp5/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/gaze16/romstage.c b/src/mainboard/system76/gaze16/romstage.c index f46e83c..119c3f5 100644 --- a/src/mainboard/system76/gaze16/romstage.c +++ b/src/mainboard/system76/gaze16/romstage.c @@ -26,5 +26,5 @@ const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/lemp10/romstage.c b/src/mainboard/system76/lemp10/romstage.c index 6a91620..749efe6 100644 --- a/src/mainboard/system76/lemp10/romstage.c +++ b/src/mainboard/system76/lemp10/romstage.c @@ -18,5 +18,5 @@ }; const bool half_populated = false; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/mainboard/system76/oryp8/romstage.c b/src/mainboard/system76/oryp8/romstage.c index affe636..64cc844 100644 --- a/src/mainboard/system76/oryp8/romstage.c +++ b/src/mainboard/system76/oryp8/romstage.c @@ -26,5 +26,5 @@ // Enable M.2 PCIE 4.0 and PEG1 mupd->FspmConfig.CpuPcieRpEnableMask = 0x3; - memcfg_init(&mupd->FspmConfig, &board_cfg, &spd_info, half_populated); + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); } diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 98482e3..6af0acc 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -109,7 +109,7 @@ uint8_t LpDdrDqDqsReTraining; }; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed); #endif /* _SOC_ALDERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index 8b54cb1..31b3ae1 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -235,11 +235,12 @@ mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); } -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated, bool *dimms_changed) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; mem_cfg->UserBd = mb_cfg->UserBd; diff --git a/src/soc/intel/tigerlake/include/soc/meminit.h b/src/soc/intel/tigerlake/include/soc/meminit.h index 6b3086c..b51c8ea 100644 --- a/src/soc/intel/tigerlake/include/soc/meminit.h +++ b/src/soc/intel/tigerlake/include/soc/meminit.h @@ -111,7 +111,7 @@ struct mem_ddr4_config ddr4_config; }; -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated); #endif /* _SOC_TIGERLAKE_MEMINIT_H_ */ diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index e8c7b68..d5ca9a9 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -147,11 +147,12 @@ mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data); } -void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, +void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dimms_changed = false; + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; if (mb_cfg->type >= ARRAY_SIZE(soc_mem_cfg)) die("Invalid memory type(%x)!\n", mb_cfg->type); -- To view, visit https://review.coreboot.org/c/coreboot/+/62736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5 Gerrit-Change-Number: 62736 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Raihow Shi (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: YH Lin, Johnny Li, Zhuohao Lee, Felix Held. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 26: (1 comment) Patchset: PS26: Hi Zhuohao, Please help to review it, thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 26 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 15 Mar 2022 10:13:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in gerrit-avatars[master]: Add avatar for 1003473
by Sean Rhodes (Code Review) 15 Mar '22

15 Mar '22

Sean Rhodes has submitted this change. ( https://review.coreboot.org/c/gerrit-avatars/+/62813 ) Change subject: Add avatar for 1003473 ...................................................................... Add avatar for 1003473 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I57f3a166565637a9b14cdb5ede82fd26be569f73 --- A 1003473.jpg 1 file changed, 0 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified; Looks good to me, approved diff --git a/1003473.jpg b/1003473.jpg new file mode 100644 index 0000000..c74869e --- /dev/null +++ b/1003473.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/62813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I57f3a166565637a9b14cdb5ede82fd26be569f73 Gerrit-Change-Number: 62813 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in gerrit-avatars[master]: Add avatar for 1003473
by Sean Rhodes (Code Review) 15 Mar '22

15 Mar '22

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/gerrit-avatars/+/62671 ) Change subject: Add avatar for 1003473 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/62671 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I6c55a754b6fef05be9a6a60a4c24273d3e10fe5e Gerrit-Change-Number: 62671 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

1 0

Change in gerrit-avatars[master]: Add avatar for 1003473
by Sean Rhodes (Code Review) 15 Mar '22

15 Mar '22

Sean Rhodes has uploaded this change for review. ( https://review.coreboot.org/c/gerrit-avatars/+/62813 ) Change subject: Add avatar for 1003473 ...................................................................... Add avatar for 1003473 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I57f3a166565637a9b14cdb5ede82fd26be569f73 --- A 1003473.jpg 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/gerrit-avatars refs/changes/13/62813/1 diff --git a/1003473.jpg b/1003473.jpg new file mode 100644 index 0000000..c74869e --- /dev/null +++ b/1003473.jpg Binary files differ -- To view, visit https://review.coreboot.org/c/gerrit-avatars/+/62813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: gerrit-avatars Gerrit-Branch: master Gerrit-Change-Id: I57f3a166565637a9b14cdb5ede82fd26be569f73 Gerrit-Change-Number: 62813 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: commonlib/timestamp_serialized: Add timestamp enum to name mapping
by Jakub Czapiga (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Julius Werner. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62709 to look at the new patch set (#5). Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping ...................................................................... commonlib/timestamp_serialized: Add timestamp enum to name mapping Some solutions require readable form of timestamps, which does not contain spaces. Current descriptive timestamp names do not meet this criteria. Also, mapping enums to their text representation allows for quick grepping (use of grep command) to find relevant timestamps in the code. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 --- M src/commonlib/include/commonlib/timestamp_serialized.h 1 file changed, 149 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/62709/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62709 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd49f20d6b00a5bbd21804cea3a50b8cef074cd1 Gerrit-Change-Number: 62709 Gerrit-PatchSet: 5 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: hp/z220_series: Convert z220_sff_workstation into variant
by Damien Zammit (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Edward O'Callaghan. Damien Zammit has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62808 ) Change subject: hp/z220_series: Convert z220_sff_workstation into variant ...................................................................... Patch Set 1: (3 comments) File src/mainboard/hp/z220_series/Kconfig: https://review.coreboot.org/c/coreboot/+/62808/comment/05aecfef_98aa66ea PS1, Line 1: BOARD_HP_Z220_SERIES > BOARD_HP_Z220_SERIES_COMMON Subjective and not strictly required. File src/mainboard/hp/z220_series/Kconfig.name: https://review.coreboot.org/c/coreboot/+/62808/comment/8477c6e5_37879917 PS1, Line 3: select BOARD_HP_Z220_SERIES > Please do selects only in Kconfig and not in Kconfig.name. See mb/siemens/chili for example. This only makes sense if there is a "base" board and variants on the base board. In this case there are two distinct mainboards. I don't want to change this. See mb/hp/snb_ivb_laptops for example. File src/mainboard/hp/z220_series/Makefile.inc: PS1: > Group the entries by stage: […] I can reorder what was already there, sure, but I was trying to minimise the diff. -- To view, visit https://review.coreboot.org/c/coreboot/+/62808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Gerrit-Change-Number: 62808 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 09:46:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: hp/z220_series: Convert z220_sff_workstation into variant
by Felix Singer (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Damien Zammit, Edward O'Callaghan. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62808 ) Change subject: hp/z220_series: Convert z220_sff_workstation into variant ...................................................................... Patch Set 1: (3 comments) File src/mainboard/hp/z220_series/Kconfig: https://review.coreboot.org/c/coreboot/+/62808/comment/838d08cf_26f64536 PS1, Line 1: BOARD_HP_Z220_SERIES BOARD_HP_Z220_SERIES_COMMON File src/mainboard/hp/z220_series/Kconfig.name: https://review.coreboot.org/c/coreboot/+/62808/comment/8acc8910_76a0504b PS1, Line 3: select BOARD_HP_Z220_SERIES Please do selects only in Kconfig and not in Kconfig.name. See mb/siemens/chili for example. File src/mainboard/hp/z220_series/Makefile.inc: PS1: Group the entries by stage: bootblock-y ... bootblock-y ... romstage-y ... romstage-y ... -- To view, visit https://review.coreboot.org/c/coreboot/+/62808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aaac75216b2d7c8bb48801454ce616ace3b1422 Gerrit-Change-Number: 62808 Gerrit-PatchSet: 1 Gerrit-Owner: Damien Zammit Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Damien Zammit Gerrit-Attention: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 09:30:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/brya/{}: Add SBU orientation property for Type C Mux
by Meera Ravindranath (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Deepti Deshatty, Prashant Malani. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61622 ) Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux ...................................................................... Patch Set 5: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/61622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7f9554b75f4d62298aac9938e66c71c3e7cee9 Gerrit-Change-Number: 61622 Gerrit-PatchSet: 5 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 09:30:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/efi: Add EFI variable store option support
by Arthur Heymans (Code Review) 15 Mar '22

15 Mar '22

Attention is currently required from: Sean Rhodes, Martin Roth, Patrick Rudolph, Jakub Czapiga, Matt DeVillier. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52564 ) Change subject: drivers/efi: Add EFI variable store option support ...................................................................... Patch Set 10: (1 comment) File src/drivers/efi/Kconfig: https://review.coreboot.org/c/coreboot/+/52564/comment/6a797622_2dd3d781 PS10, Line 1: DRIVERS_EFI_VARIABLE_STORE Should it select the right UDK to get the UEFI headers? -- To view, visit https://review.coreboot.org/c/coreboot/+/52564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8079f71d29da5dc2db956fc68bef1486fe3906bb Gerrit-Change-Number: 52564 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 15 Mar 2022 09:24:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022