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Curtis Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62727 )
Change subject: soc/intel/alderlake: Update ADL-P id list of th VccIn Aux Imon IccMax values
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62727/comment/f2549458_560cda33
PS1, Line 12: TEST=Build and check fsp log to confirm the settings are set properly.
> Please add […]
Done
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Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62315 )
Change subject: mb/google/dedede/var/galtic: Add fw_config probe for 2nd touchscreen
......................................................................
Patch Set 4: Code-Review+1
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Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62360
to look at the new patch set (#16).
Change subject: mb/google/cherry: Add PCIe domain support
......................................................................
mb/google/cherry: Add PCIe domain support
Add override device tree for dojo and add PCIe domain support.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972
---
M src/mainboard/google/cherry/Kconfig
A src/mainboard/google/cherry/variants/dojo/overridetree.cb
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/16
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Hello Hung-Te Lin, Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62800
to look at the new patch set (#2).
Change subject: soc/mediatek: PCI: Remove global variable
......................................................................
soc/mediatek: PCI: Remove global variable
Remove global variable and use 'pcidev_path_on_root()' to get the base
address of PCIe controller.
TEST=Build pass and boot up to kernel successfully via SSD on Dojo
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x15b7
PCI SSVID : 0x15b7
SN : 21517J440114
MN : WDC PC SN530 SDBPTPZ-256G-1006
RAB : 0x4
AERL : 0x7
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ia41c82a7aa5d6e9d936e242550851cef83afeae9
---
M src/soc/mediatek/common/pcie.c
1 file changed, 29 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/62800/2
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