Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 )
Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Does Jenkins not build that configuration? I wonder if it's using the legacy SMM flow.
Looking at the Jenkins results: https://qa.coreboot.org/job/coreboot-gerrit/198387/testReport/board/
It shows we are only building chromeos variants? Is that expected? It also looks like we are building `EMULATION_QEMU_X86_Q35`, but it doesn't have DEBUG_SMI.
https://review.coreboot.org/c/coreboot/+/62793 should fix it. Can you try it out?
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 )
Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> This breaks on qemu when enabling CONFIG_CONSOLE_CBMEM and DEBUG_SMI […]
Does Jenkins not build that configuration? I wonder if it's using the legacy SMM flow.
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62739 )
Change subject: mb/google/brya: set GPP_D0 to GPO and unlocked
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/baseboard/brya/gpio.c:
https://review.coreboot.org/c/coreboot/+/62739/comment/639d697a_eba7d2d0
PS4, Line 121: PAD_CFG_GPO
> looks like it worked with GPO_LOCK, please update the CL.
Oh yes flash_fp_mcu is setting the MODE bits to OUTPUT, so it needs to be set explicitly here
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Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
Patch Set 42:
(1 comment)
File src/drivers/intel/fsp2_0/include/fsp/util.h:
https://review.coreboot.org/c/coreboot/+/59638/comment/b76edad8_c3891d70
PS38, Line 34: __packed
> Drop this. […]
Ack
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Subrata Banik has uploaded a new patch set (#42) to the change originally created by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/59638 )
Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
......................................................................
drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
FSP 2.3 spec introduced FSP_NON_VOLATILE_STORAGE_HOB2 HOB version
for NV data storage. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated
from FSP 2.3 onwards and is maintained for backward compatibility only.
This patch implements the parsing method for
FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first
searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue
to search for FSP_NON_VOLATILE_STORAGE_HOB HOB.
Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com>
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e
---
M src/drivers/intel/fsp2_0/hand_off_block.c
M src/drivers/intel/fsp2_0/include/fsp/util.h
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/59638/42
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Change subject: soc/intel/tgl: move DIMM_SPD_SIZE from mb to SoC Kconfig
......................................................................
Patch Set 2: Code-Review+1
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/12471 )
Change subject: device/device.c: remove warning for missing apic read resources
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/12471/comment/52b46b1d_9828ff0c
PS2, Line 9: We have had the "APIC: 00 missing read_resources" messages
> Martin & Nico, we're seeing similar errors on MediaTek platforms: […]
I found this devicetree in google/corsola. Looking at the soc code, I couldn't
find how the `cpu` device is used. Even the `cpu_cluster` only gets general
soc functions attached, AFAICT. Maybe I missed something, though.
So, what I wonder: Does the `device cpu` line in the devicetree do anything
beside causing that error message?
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62787
to look at the new patch set (#2).
Change subject: include/efi: Clean up efi_datatype.h file
......................................................................
include/efi: Clean up efi_datatype.h file
This patch cleans up `efi_datatype.h` to allow other SoC and/or driver
code to use this file.
`PiPei.h` file only gets added from UDK2017 hence, the platform with the
older EDK2 base (prior to UDK2017) is unable to resolve this file
dependency.
This CL removed the `PiPei.h` header and only added the required header
file `PiPeiCis.h` for platforms with UDK base >= 2017.
TEST=Able to build Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie9177814fcf41e5950ace94050356f0273f765c5
---
M src/include/efi/efi_datatype.h
1 file changed, 9 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62787/2
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