coreboot-gerrit March 2022

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Change in coreboot[master]: payloads/tianocore: Add missing CONFIG_
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Sean Rhodes, Martin Roth. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62920 ) Change subject: payloads/tianocore: Add missing CONFIG_ ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f4aa0286a77f6c94b5e5ec97a0034ea7594b4f Gerrit-Change-Number: 62920 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 09:12:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Angel Pons, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... Patch Set 18: (1 comment) File src/mainboard/google/cherry/variants/dojo/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62360/comment/161295b1_81397200 PS18, Line 6: .base = 0x112f0000, Add a comment in the commit message, where the values are from? -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 09:10:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Angel Pons, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62360 ) Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... Patch Set 18: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62360/comment/73b2e61e_831aeb96 PS18, Line 7: mb/google/cherry: Add PCIe domain support Add *dojo* somewhere? https://review.coreboot.org/c/coreboot/+/62360/comment/91084aae_8b7b64d8 PS18, Line 9: Add override device tree for dojo and add PCIe domain support. So not all variants of google/cherry are going to support PCIe? -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 09:10:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Angel Pons, Yu-Ping Wu, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62933/comment/22dd4518_f9777714 PS1, Line 10: Also paste the new log messages? File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/62933/comment/c5f74e05_7cd2c11a PS1, Line 239: pre_timestamp, cur_timestamp, perst_time Append unit us to the name, or is that clear? For example `perst_time_us`. https://review.coreboot.org/c/coreboot/+/62933/comment/364af3d9_bc8cff5f PS1, Line 245: [%lld] Brackets not needed? https://review.coreboot.org/c/coreboot/+/62933/comment/c2f40ac4_0689c98f PS1, Line 255: [%lld] Ditto. -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 09:08:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCIe: Assert PERST# at bootblock stage
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Shelley Chen, Rex-BC Chen, Angel Pons, Yu-Ping Wu, Jianjun Wang. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCIe: Assert PERST# at bootblock stage ...................................................................... Patch Set 18: (3 comments) Patchset: PS18: Reading the commit message, and then the diff, I am a little confused. Maybe state somewhere, that the preinit only does the assert? File src/mainboard/google/cherry/bootblock.c: https://review.coreboot.org/c/coreboot/+/62359/comment/73c1dd36_27eaa355 PS18, Line 48: mtk_pcie_pre_init(); So, this needs to be done for each mainboard, and cannot be done in SOC code? File src/soc/mediatek/mt8195/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62359/comment/4c930cf4_98da4303 PS18, Line 11: bootblock-$(CONFIG_PCI) += pcie.c This could be a separate commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 09:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: tests/lib: Add space before single line comment termination
by Paul Menzel (Code Review) 19 Mar '22

19 Mar '22

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62935 ) Change subject: tests/lib: Add space before single line comment termination ...................................................................... tests/lib: Add space before single line comment termination Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M tests/lib/bootmem-test.c M tests/lib/imd-test.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/62935/1 diff --git a/tests/lib/bootmem-test.c b/tests/lib/bootmem-test.c index 6059833..ddd62ae 100644 --- a/tests/lib/bootmem-test.c +++ b/tests/lib/bootmem-test.c @@ -311,7 +311,7 @@ ret = bootmem_region_targets_type(RAMSTAGE_START, RAMSTAGE_SIZE, BM_MEM_RESERVED); assert_int_equal(ret, 0); - /* Range covering one more byte than one region*/ + /* Range covering one more byte than one region */ ret = bootmem_region_targets_type(RAMSTAGE_START, RAMSTAGE_SIZE + 1, BM_MEM_RAMSTAGE); assert_int_equal(ret, 0); diff --git a/tests/lib/imd-test.c b/tests/lib/imd-test.c index 28a4456..de42e08 100644 --- a/tests/lib/imd-test.c +++ b/tests/lib/imd-test.c @@ -49,7 +49,7 @@ struct imd imd; uintptr_t test_inputs[] = { 0, /* Lowest possible address */ - 0xA000, /* Fits in 16 bits, should not get rounded down*/ + 0xA000, /* Fits in 16 bits, should not get rounded down */ 0xDEAA, /* Fits in 16 bits */ 0xB0B0B000, /* Fits in 32 bits, should not get rounded down */ 0xF0F0F0F0, /* Fits in 32 bits */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9321391cc06afddff94fbba79f93851b553c74b1 Gerrit-Change-Number: 62935 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp
by Hung-Te Lin (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62934 ) Change subject: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: In comparison to a single region with 8 bytes only, I'd rather make it a generic feature for passing data across sessions, especially for early init. This can be useful if someday we have to build up a general framework for eMMC, NVMe, and UFS. What about struct mtk_early_init { u64 pcie_timestamp; } *mtk_early_init; And REGION(MTK_EARLY_INIT) In bootblock, initialize that to all empty; struct mtk_early_init *find_early_init() { static_assert(sizeof(struct mtk_early_init) <= REGION_SIZE(mtk_early_init)); return _mtk_early_init; } void reset_early_init() { struct mtk_early_init *p = find_early_init(); if (!p) return; memset(mtk_early_init, 0, sizeof(*mtk_early_init)); } There can even be a general early_init.c in common for reset_early_init(); , in pcie_preinit do find_early_init() then update pcie_timestamp to a timestamp, and in NVMe driver, find_early_init(), check if pcie_timestamp is non-zero (if zero, sleep enough time assuming the pre_init was never done), and sleep() by calculating pcie_timestamp. -- To view, visit https://review.coreboot.org/c/coreboot/+/62934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia97468742e144d8343f5c7ae6db7cb82a316cf5c Gerrit-Change-Number: 62934 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 08:33:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: PCIe: Assert PERST# at bootblock stage
by Hung-Te Lin (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Shelley Chen, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62359 ) Change subject: soc/mediatek: PCIe: Assert PERST# at bootblock stage ...................................................................... Patch Set 18: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62359/comment/81c8ba6d_c32553db PS18, Line 32: Please add BRANCH=cherry After BUG=XXX, for all patches related to mt8195 or PCIe. -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 08:14:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp
by Hung-Te Lin (Code Review) 19 Mar '22

19 Mar '22

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Change in coreboot[master]: soc/intel/common: Configure TCSS access through IOE P2SB
by Eric Lai (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Subrata Banik, John Zhao, Tim Wawrzynczak, Paul Menzel, Angel Pons, Patrick Rudolph, EricR Lai. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62723 ) Change subject: soc/intel/common: Configure TCSS access through IOE P2SB ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 9 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: John Zhao <john.zhao(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 05:46:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022