coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp
by Jianjun Wang (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Hung-Te Lin. Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62934 ) Change subject: soc/mediatek/mt8195: Reserve memory to store PCIe timestamp ...................................................................... soc/mediatek/mt8195: Reserve memory to store PCIe timestamp Reserve 8 byte space from SRAM to store the timestamp of PCIe. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ia97468742e144d8343f5c7ae6db7cb82a316cf5c --- M src/soc/mediatek/mt8195/include/soc/memlayout.ld M src/soc/mediatek/mt8195/include/soc/symbols.h 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/62934/1 diff --git a/src/soc/mediatek/mt8195/include/soc/memlayout.ld b/src/soc/mediatek/mt8195/include/soc/memlayout.ld index 5942776..7a05e3b 100644 --- a/src/soc/mediatek/mt8195/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8195/include/soc/memlayout.ld @@ -19,6 +19,10 @@ _ = ASSERT(size % 4K == 0, \ "DRAM DMA buffer should be multiple of smallest page size (4K)!"); +#define PCIE_TIMESTAMP(addr, size) \ + REGION(pcie_timestamp, addr, size, 4) \ + _ = ASSERT(size == 8, "PCIe timestamp should be exactly 8 byte!"); + SECTIONS { SRAM_START(0x00100000) @@ -26,6 +30,7 @@ TPM_TCPA_LOG(0x00103000, 2K) FMAP_CACHE(0x00103800, 2K) WATCHDOG_TOMBSTONE(0x00104000, 4) + PCIE_TIMESTAMP(0x00104004, 8) CBFS_MCACHE(0x00107c00, 8K) TIMESTAMP(0x00109c00, 1K) STACK(0x0010a000, 12K) diff --git a/src/soc/mediatek/mt8195/include/soc/symbols.h b/src/soc/mediatek/mt8195/include/soc/symbols.h index 76d9c6d..eeb466d 100644 --- a/src/soc/mediatek/mt8195/include/soc/symbols.h +++ b/src/soc/mediatek/mt8195/include/soc/symbols.h @@ -5,5 +5,6 @@ #include <symbols.h> DECLARE_REGION(dram_dma) +DECLARE_REGION(pcie_timestamp) #endif /* _SOC_MEDIATEK_MT8195_SYMBOLS_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62934 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia97468742e144d8343f5c7ae6db7cb82a316cf5c Gerrit-Change-Number: 62934 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Jianjun Wang (Code Review) 19 Mar '22

19 Mar '22

Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62933 ) Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... soc/mediatek: Add timestamp to measure PERST# time Add timestamp support to measure the assertion time of PERST#. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/common/pcie.c 2 files changed, 34 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/62933/1 diff --git a/src/mainboard/google/cherry/bootblock.c b/src/mainboard/google/cherry/bootblock.c index dd83817..f5839ab 100644 --- a/src/mainboard/google/cherry/bootblock.c +++ b/src/mainboard/google/cherry/bootblock.c @@ -1,12 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <bootblock_common.h> +#include <console/console.h> #include <device/mmio.h> #include <gpio.h> #include <soc/gpio.h> #include <soc/i2c.h> #include <soc/pcie.h> #include <soc/spi.h> +#include <soc/symbols.h> +#include <timestamp.h> #include "gpio.h" @@ -44,9 +47,16 @@ void bootblock_mainboard_init(void) { - if (CONFIG(PCI)) + if (CONFIG(PCI)) { mtk_pcie_pre_init(); + if (CONFIG(COLLECT_TIMESTAMPS) && + REGION_SIZE(pcie_timestamp) > 0) { + uint64_t timestamp = timestamp_get(); + write64(_pcie_timestamp, timestamp); + } + } + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); nor_set_gpio_pinmux(); diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index c46b53f..839ff56 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -14,7 +14,9 @@ #include <soc/pcie.h> #include <soc/pcie_common.h> #include <soc/soc_chip.h> +#include <soc/symbols.h> #include <stdlib.h> +#include <timestamp.h> #include <types.h> #define PCIE_SETTING_REG 0x80 @@ -233,6 +235,27 @@ val &= ~PCIE_INTX_ENABLE; write32p(conf->base + PCIE_INT_ENABLE_REG, val); + if (CONFIG(COLLECT_TIMESTAMPS) && REGION_SIZE(pcie_timestamp) > 0) { + uint64_t pre_timestamp, cur_timestamp, perst_time; + + pre_timestamp = read64(_pcie_timestamp); + cur_timestamp = timestamp_get(); + perst_time = cur_timestamp - pre_timestamp; + + printk(BIOS_DEBUG, "%s: [%lld] us elapsed since assert PERST#\n", + __func__, perst_time); + + /* + * Described in PCIe CEM specification sections 2.2 + * (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). + * The deassertion of PERST# should be delayed 100ms (TPVPERL) + * for the power and clock to become stable. + */ + if (perst_time < 100000) + printk(BIOS_WARNING, "%s: PERST# assert time [%lld] us may not enough for link up\n", + __func__, perst_time); + } + /* De-assert reset signals */ mtk_pcie_reset(conf->base + PCIE_RST_CTRL_REG, false); -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek: PCIe: Assert PERST# at bootblock stage
by Jianjun Wang (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Rex-BC Chen, Paul Menzel, Angel Pons, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62359 to look at the new patch set (#18). Change subject: soc/mediatek: PCIe: Assert PERST# at bootblock stage ...................................................................... soc/mediatek: PCIe: Assert PERST# at bootblock stage Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and wait for 100ms, assert the pin in bootblock stage so that the extra 100ms delay could be avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d --- M src/mainboard/google/cherry/bootblock.c M src/soc/mediatek/mt8195/Makefile.inc 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 18 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/p2sb: Add helper function to enable BAR
by Subrata Banik (Code Review) 19 Mar '22

19 Mar '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62778 ) Change subject: soc/intel/common/block/p2sb: Add helper function to enable BAR ...................................................................... soc/intel/common/block/p2sb: Add helper function to enable BAR This patch creates a new helper function to enable P2SB BAR. `p2sb_dev_enable_bar()` takes the PCI P2SB device address (B/D/F) and BAR address (combining high and low base addresses). BUG=b:224325352 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62778 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/p2sblib.h M src/soc/intel/common/block/p2sb/Makefile.inc M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/p2sb/p2sblib.c 4 files changed, 14 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h index 7df528d2..9f6b97d 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sblib.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h @@ -10,6 +10,7 @@ #define P2SBC 0xe0 #define P2SBC_HIDE_BIT (1 << 0) +void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar); bool p2sb_dev_is_hidden(pci_devfn_t dev); void p2sb_dev_unhide(pci_devfn_t dev); void p2sb_dev_hide(pci_devfn_t dev); diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index dbf4545..f051120 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,3 +1,5 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c +romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB) += p2sblib.c diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 94db33d..1b0c080 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -18,13 +18,7 @@ void p2sb_enable_bar(void) { - /* Enable PCR Base address in PCH */ - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_0, P2SB_BAR); - pci_write_config32(PCH_DEV_P2SB, PCI_BASE_ADDRESS_1, 0); - - /* Enable P2SB MSE */ - pci_write_config16(PCH_DEV_P2SB, PCI_COMMAND, - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + p2sb_dev_enable_bar(PCH_DEV_P2SB, P2SB_BAR); } /* diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c index faef79a..e1a5bc2 100644 --- a/src/soc/intel/common/block/p2sb/p2sblib.c +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -10,6 +10,16 @@ #include <intelblocks/pcr.h> #include <soc/pci_devs.h> +void p2sb_dev_enable_bar(pci_devfn_t dev, uint64_t bar) +{ + /* Enable PCR Base addresses */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, (uint32_t)bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, (uint32_t)(bar >> 32)); + + /* Enable P2SB MSE */ + pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + bool p2sb_dev_is_hidden(pci_devfn_t dev) { const uint16_t pci_vid = pci_read_config16(dev, PCI_VENDOR_ID); 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica41e8e8bdfcfe855e730b3878b874070062ef93 Gerrit-Change-Number: 62778 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: payloads/tianocore: Add missing CONFIG_
by Stefan Reinauer (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Sean Rhodes, Martin Roth. Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62920 ) Change subject: payloads/tianocore: Add missing CONFIG_ ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88f4aa0286a77f6c94b5e5ec97a0034ea7594b4f Gerrit-Change-Number: 62920 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 05:14:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid
by Felix Held (Code Review) 19 Mar '22

19 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62002 ) Change subject: mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid ...................................................................... mb/google/dedede/var/lantis: Add ELAN touchscreen support for Landrid The touchscreen slave address for landrid is 0x10 same as lantis, so we use SSFC to switch touchscreen controller. BUG=b:222976965 TEST=emerge-dedede coreboot Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906 Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/lantis/overridetree.cb 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/dedede/variants/lantis/overridetree.cb b/src/mainboard/google/dedede/variants/lantis/overridetree.cb index 3a9910b..3ba85bd 100644 --- a/src/mainboard/google/dedede/variants/lantis/overridetree.cb +++ b/src/mainboard/google/dedede/variants/lantis/overridetree.cb @@ -4,6 +4,11 @@ option AUDIO_CODEC_ALC5682 1 option AUDIO_CODEC_ALC5682I_VS 2 end + field TS_DRIVER_SOURCE 43 45 + option TS_UNPROVISIONED 0 + option TS_ELAN0001 1 + option TS_ELAN2513 2 + end end chip soc/intel/jasperlake @@ -176,7 +181,25 @@ register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" register "enable_delay_ms" = "1" register "has_power_resource" = "1" - device i2c 10 on end + device i2c 10 on + probe TS_DRIVER_SOURCE TS_UNPROVISIONED + probe TS_DRIVER_SOURCE TS_ELAN0001 + end + end + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D4_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D5)" + register "generic.reset_delay_ms" = "20" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D6)" + register "generic.enable_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe TS_DRIVER_SOURCE TS_ELAN2513 + end end chip drivers/i2c/hid register "generic.hid" = ""GTCH7503"" -- To view, visit https://review.coreboot.org/c/coreboot/+/62002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23d3de5e45aa2876c1590a1e09679d652a3f2906 Gerrit-Change-Number: 62002 Gerrit-PatchSet: 16 Gerrit-Owner: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/cbmem: Keep original Total Time calculation when no negative tim...
by Julius Werner (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Bora Guvendik, Subrata Banik, Maulik V Vaghela, Selma Bensaid, Tim Wawrzynczak. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61839 ) Change subject: util/cbmem: Keep original Total Time calculation when no negative timestamps ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0442f796b03731df3b869aea32d40ed94cabdce0 Gerrit-Change-Number: 61839 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Sat, 19 Mar 2022 01:03:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Robert Zieba (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Raul Rangel, Reka Norman, Nick Vaccaro, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Patch Set 7: (1 comment) File util/spd_tools/src/part_id_gen/part_id_gen.go: https://review.coreboot.org/c/coreboot/+/62905/comment/c6ef7029_099b81c4 PS5, Line 332: && > Unfortunately this wouldn't result in the right behavior. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 00:09:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Robert Zieba <robertzieba(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Robert Zieba (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Raul Rangel, Reka Norman, Nick Vaccaro, Karthik Ramasubramanian. Robert Zieba has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Patch Set 7: (2 comments) File util/spd_tools/src/part_id_gen/part_id_gen.go: https://review.coreboot.org/c/coreboot/+/62905/comment/a37c9ee6_e1ae2484 PS5, Line 332: && > From consistency standpoint, can we add Exclusive entries to SPDToIndexMap. […] Unfortunately this wouldn't result in the right behavior. If an exclusive entry is present in SPDToIndexMap then the auto-assigning code will continue through line 384 resulting in the part at that index getting overwritten. Additionally, attempting to use both Fixed and Exclusive with the same slot is an error. https://review.coreboot.org/c/coreboot/+/62905/comment/b33bb494_7ee84486 PS5, Line 359: if index < len(assignedMapping) { : mapping = assignedMapping[index] : } > This check can be removed if you append assignedMapping after line 385: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Sat, 19 Mar 2022 00:08:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Robert Zieba (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Reka Norman, Nick Vaccaro. Hello build bot (Jenkins), Raul Rangel, Bhanu Prakash Maiya, Reka Norman, Nick Vaccaro, Karthik Ramasubramanian, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62905 to look at the new patch set (#7). Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... util/spd_tools: Add support for exclusive IDs Currently memory parts that use the same SPD are assigned the same ID by spd_tools. This commit adds support for exclusive IDs. When given an exclusive ID a memory part will not share its ID with other parts unless they have also have the same exclusive ID. BUG=b:225161910 TEST=Ran part_id_gen and checked that exclusive IDs work correctly and that the current behavior still works in their abscence. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 --- M util/spd_tools/README.md M util/spd_tools/src/part_id_gen/part_id_gen.go 2 files changed, 62 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62905/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022