coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/guybrush/port_descriptors: use enum values for link speed
by Felix Held (Code Review) 19 Mar '22

19 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62908 ) Change subject: mb/google/guybrush/port_descriptors: use enum values for link speed ...................................................................... mb/google/guybrush/port_descriptors: use enum values for link speed Use GEN3 from enum dxio_link_speed_cap instead of the number 3. TEST=Timeless build results in identical firmware image for guybrush Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62908 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/guybrush/port_descriptors.c 1 file changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/port_descriptors.c b/src/mainboard/google/guybrush/port_descriptors.c index 158a802..040298b 100644 --- a/src/mainboard/google/guybrush/port_descriptors.c +++ b/src/mainboard/google/guybrush/port_descriptors.c @@ -14,7 +14,7 @@ .port_present = true, .start_logical_lane = 0, .end_logical_lane = 0, - .link_speed_capability = 3, + .link_speed_capability = GEN3, .device_number = PCI_SLOT(WLAN_DEVFN), .function_number = PCI_FUNC(WLAN_DEVFN), .link_aspm = ASPM_L1, @@ -29,7 +29,7 @@ .port_present = true, .start_logical_lane = 1, .end_logical_lane = 1, - .link_speed_capability = 3, + .link_speed_capability = GEN3, .device_number = PCI_SLOT(SD_DEVFN), .function_number = PCI_FUNC(SD_DEVFN), .link_aspm = ASPM_L1, @@ -45,7 +45,7 @@ .port_present = true, .start_logical_lane = 2, .end_logical_lane = 2, - .link_speed_capability = 3, + .link_speed_capability = GEN3, .device_number = PCI_SLOT(WWAN_DEVFN), .function_number = PCI_FUNC(WWAN_DEVFN), .link_aspm = ASPM_L1, @@ -60,7 +60,7 @@ .port_present = true, .start_logical_lane = 4, .end_logical_lane = 7, - .link_speed_capability = 3, + .link_speed_capability = GEN3, .device_number = PCI_SLOT(NVME_DEVFN), .function_number = PCI_FUNC(NVME_DEVFN), .link_aspm = ASPM_L1, -- To view, visit https://review.coreboot.org/c/coreboot/+/62908 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0dddc57e05ec2395ca980bb63320bb9ee5242c29 Gerrit-Change-Number: 62908 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne: Turn off gpp clock request for disabled devices
by Felix Held (Code Review) 19 Mar '22

19 Mar '22

Attention is currently required from: Robert Zieba, Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61259 ) Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices ...................................................................... Patch Set 34: (3 comments) File src/soc/amd/cezanne/fch.c: https://review.coreboot.org/c/coreboot/+/61259/comment/088ec307_ceef9a6d PS34, Line 183: assert(gpp_req_index >= 0 && gpp_req_index < gpp_clk_config_num); by default asserts aren't fatal, so it'll complain but still continue; not sure if this is intended here. i'd check this and if the conditions aren't met, print a warning/info and do a continue to not run the rest of the code in the loop. https://review.coreboot.org/c/coreboot/+/61259/comment/3c9305c4_6a769007 PS34, Line 196: /* PCIe devices haven't been fully set up yet, so directly read the vendor id the code below reads both the vendor and product id; both ids are just 16 bit with the vendor id starting at 0x00 and the device id starting at 0x02. the code behaves as i'd expect, but the comment should mention the device id too https://review.coreboot.org/c/coreboot/+/61259/comment/90ed5664_813c3241 PS34, Line 200: && (id != 0x0000ffff) && (id != 0xffff0000) not sure if those two cases are needed. if something doesn't get decoded i'd expect it to return all-ones. all-zeros might also be failure case. vendor id all-ones and device id all-zeros or vice versa looks like an odd failure case to me. checking those cases too shouldn't hurt, but looked a bit unexpected to me -- To view, visit https://review.coreboot.org/c/coreboot/+/61259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c Gerrit-Change-Number: 61259 Gerrit-PatchSet: 34 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 22:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Configure TCSS access through IOE P2SB
by John Zhao (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Paul Menzel, Angel Pons, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Subrata Banik, Wonkyu Kim, Eric Lai, Angel Pons, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62723 to look at the new patch set (#9). Change subject: soc/intel/common: Configure TCSS access through IOE P2SB ...................................................................... soc/intel/common: Configure TCSS access through IOE P2SB This change abstracts the TCSS access through IOE P2SB on Meteor Lake. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/cfg.h M src/soc/intel/common/block/include/intelblocks/tcss.h M src/soc/intel/common/block/tcss/Kconfig M src/soc/intel/common/block/tcss/tcss.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/fsp_params.c 9 files changed, 57 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62723/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/62723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b Gerrit-Change-Number: 62723 Gerrit-PatchSet: 9 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts
by Karthik Ramasubramanian (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Bhanu Prakash Maiya, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62930 ) Change subject: mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Please update 3rdparty/blobs/mainboard/google/guybrush/APCB_CZN_D4.bin with the one generated from the chromium tree. This is required to address the build bot failure. -- To view, visit https://review.coreboot.org/c/coreboot/+/62930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Gerrit-Change-Number: 62930 Gerrit-PatchSet: 2 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 18 Mar 2022 21:51:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/spd_tools: Add support for exclusive IDs
by Karthik Ramasubramanian (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Robert Zieba, Raul Rangel, Reka Norman, Nick Vaccaro. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62905 ) Change subject: util/spd_tools: Add support for exclusive IDs ...................................................................... Patch Set 6: (2 comments) File util/spd_tools/src/part_id_gen/part_id_gen.go: https://review.coreboot.org/c/coreboot/+/62905/comment/eebf7e9c_080fc333 PS5, Line 332: && From consistency standpoint, can we add Exclusive entries to SPDToIndexMap. You can update the condition as follows: if SPDToIndexMap[SPDFileName] < 0 || p.mapping != Exclusive { SPDToIndexMap[SPDFileName] = p.index } The or condition allows Fixed entries to overwrite the Exclusive entries in that map. https://review.coreboot.org/c/coreboot/+/62905/comment/db76027c_391689c1 PS5, Line 359: if index < len(assignedMapping) { : mapping = assignedMapping[index] : } This check can be removed if you append assignedMapping after line 385: ``` partIdList = append(partIdList, partIds{}) assignedMapping = append(assignedMapping, Auto) ``` Then you can combine the remaining if blocks into one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62905 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8 Gerrit-Change-Number: 62905 Gerrit-PatchSet: 6 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 21:46:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: src/driver/wifi: Add _DSM method for DDRRFIM
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Tim Wawrzynczak. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61020 ) Change subject: src/driver/wifi: Add _DSM method for DDRRFIM ...................................................................... Patch Set 20: (1 comment) File src/drivers/wifi/generic/acpi.c: https://review.coreboot.org/c/coreboot/+/61020/comment/9f5412aa_12d83a80 PS20, Line 539: dev = dev->link_list->children; : const struct drivers_wifi_generic_config *config = dev->chip_info; : if (dev) { child device should already be passed in to this function now if you rebase on master -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 20 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 21:42:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Add GPU power sequencing
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Subrata Banik, Angel Pons, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62384 ) Change subject: mb/google/brya/var/agah: Add GPU power sequencing ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/variants/agah/variant.c: https://review.coreboot.org/c/coreboot/+/62384/comment/84e58f01_6922d937 PS1, Line 104: void variant_finalize(void) > I wonder, is this called before or after the `save_pci_bars_to_acpi` setting is honored? was called before, but it's fine, because the resources are saved into coreboot data structures -- To view, visit https://review.coreboot.org/c/coreboot/+/62384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88 Gerrit-Change-Number: 62384 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 21:21:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Add variant_init and variant_finalize callbacks
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Attention is currently required from: Subrata Banik, Angel Pons, Nick Vaccaro. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62382 ) Change subject: mb/google/brya: Add variant_init and variant_finalize callbacks ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/mainboard.c: https://review.coreboot.org/c/coreboot/+/62382/comment/a6a30375_54801539 PS1, Line 72: : void __weak variant_finalize(void) > `variant_devtree_update()` would also need to be updated to be consistent, I'd suggest making a foll […] We are consistently inconsistent. -- To view, visit https://review.coreboot.org/c/coreboot/+/62382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20 Gerrit-Change-Number: 62382 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 18 Mar 2022 21:19:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASL
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62932 ) Change subject: mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASL ...................................................................... mb/google/brya/var/agah: Select INCLUDE_NVIDIA_GPU_ASL The agah variant will include an Nvidia GN20 series GPU, therefore select the INCLUDE_NVIDIA_GPU_ASL Kconfig to include the respective ASL code into the DSDT. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9 --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/62932/1 diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index e29ef9f..cbfa508 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -4,6 +4,7 @@ bool "-> Agah" select BOARD_GOOGLE_BASEBOARD_BRYA select DRIVERS_I2C_MAX98390 + select INCLUDE_NVIDIA_GPU_ASL select PCIEXP_SUPPORT_RESIZABLE_BARS select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD -- To view, visit https://review.coreboot.org/c/coreboot/+/62932 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icc718d01506ccb4dd42841239e96926f4ddaa9c9 Gerrit-Change-Number: 62932 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support
by Tim Wawrzynczak (Code Review) 18 Mar '22

18 Mar '22

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62931 ) Change subject: mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support ...................................................................... mb/google/brya/: Add PEG and initial Nvidia dGPU ASL support Some brya variants will use a GN20 series Nvidia GPU, which requires quite a bit of ACPI support code to be written for it. This patch lands a decent bit of the initial code for it on the brya platform, including: 1) PEG RTD3 methods 2) DGPU power operations (RTD3 and GCOFF, NVJT _DSM and other Methods) 3) NVOP _DSM method There will be more support to come later, this is all written to specifications from the Nvidia Software Design Guide for GN20. BUG=b:214581763 TEST=build patch train Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 --- M src/mainboard/google/brya/Kconfig A src/mainboard/google/brya/acpi/gpu_top.asl A src/mainboard/google/brya/acpi/nvjt.asl A src/mainboard/google/brya/acpi/nvop.asl A src/mainboard/google/brya/acpi/peg.asl A src/mainboard/google/brya/acpi/power.asl A src/mainboard/google/brya/acpi/utility.asl M src/mainboard/google/brya/dsdt.asl 8 files changed, 713 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/62931/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 1d29b6f..a7435b9 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -252,4 +252,9 @@ config HAVE_SLP_S0_GATE def_bool n +config INCLUDE_NVIDIA_GPU_ASL + def_bool n + help + Select this if the variant has an Nvidia GN20 GPU attached to PEG1 + endif # BOARD_GOOGLE_BRYA_COMMON diff --git a/src/mainboard/google/brya/acpi/gpu_top.asl b/src/mainboard/google/brya/acpi/gpu_top.asl new file mode 100644 index 0000000..b893ed5 --- /dev/null +++ b/src/mainboard/google/brya/acpi/gpu_top.asl @@ -0,0 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NV_ERROR_SUCCESS 0x0 +#define NV_ERROR_UNSPECIFIED 0x80000001 +#define NV_ERROR_UNSUPPORTED 0x80000002 + +#define PCI_OWNER_SBIOS 0x0 +#define PCI_OWNER_DRIVER 0x1 + +#define OPTIMUS_POWER_CONTROL_DISABLE 0x2 +#define OPTIMUS_POWER_CONTROL_ENABLE 0x3 + +#define OPTIMUS_CONTROL_NO_RUN_PS0 0x0 +#define OPTIMUS_CONTROL_RUN_PS0 0x1 + +#define GC6_STATE_EXITED 0x0 +#define GC6_STATE_ENTERED 0x1 +#define GC6_STATE_TRANSITION 0x2 + +#define GC6_DEFER_DISABLE 0x0 +#define GC6_DEFER_ENABLE 0x1 + +#define NOTIFY_GPS_EVENT_STATUS_CHANGE 0xc0 +#define NOTIFY_GPS_NVPCF_STATUS_CHANGE 0xc5 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_0 0xd1 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_1 0xd2 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_2 0xd3 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_3 0xd4 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_4 0xd5 + +#define UUID_NVOP "a486d8f8-0bda-471b-a72b-6042a6b5bee0" +#define UUID_NVJT "cbeca351-067b-4924-9cbd-b46b00b86f34" + +#define REVISION_MIN_NVOP 0x100 +#define REVISION_MIN_NVJT 0x100 + +#define NVJT_GPC_GSS 0 +#define NVJT_GPC_EGNS 1 +#define NVJT_GPC_EGIS 2 +#define NVJT_GPS_XGXS 3 +#define NVJT_GPS_XGIS 4 + +Scope (\_SB.PCI0.PEG1) +{ + Device (PEGP) + { + Name (_ADR, 0x0) + OperationRegion (PCIC, PCI_Config, 0x00, 0x100) + Field (PCIC, DWordAcc, NoLock, Preserve) + { + VGAR, 2048, /* VGA Registers */ + } + + #include "utility.asl" + #include "power.asl" + #include "nvop.asl" + #include "nvjt.asl" + + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID (UUID_NVOP)) + { + If (ToInteger(Arg1) >= REVISION_MIN_NVOP) + { + Return (NVOP(Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_NVJT)) + { + If (ToInteger (Arg1) >= REVISION_MIN_NVJT) + { + Return (NVJT (Arg2, Arg3)) + } + } + + Return (NV_ERROR_UNSUPPORTED) + } + } + + #include "peg.asl" +} diff --git a/src/mainboard/google/brya/acpi/nvjt.asl b/src/mainboard/google/brya/acpi/nvjt.asl new file mode 100644 index 0000000..200bcc3 --- /dev/null +++ b/src/mainboard/google/brya/acpi/nvjt.asl @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define JT_FUNC_SUPPORT 0 +#define JT_FUNC_CAPS 1 +#define JT_FUNC_POWERCONTROL 2 +#define JT_FUNC_PLATPOLICY 3 + +Method (NVJT, 2, Serialized) +{ + Switch (ToInteger(Arg0)) + { + Case (JT_FUNC_SUPPORT) + { + Return (ITOB( + (1 << JT_FUNC_SUPPORT) | + (1 << JT_FUNC_CAPS) | + (1 << JT_FUNC_POWERCONTROL) | + (1 << JT_FUNC_PLATPOLICY))) + } + Case (JT_FUNC_CAPS) + { + Return (ITOB( + (0 << 0) | /* JTE: G-Sync NVSR Power Features Enabled */ + (1 << 0) | /* NVSE: NVSR Disabled */ + (0 << 3) | /* PPR: Panel Power Rail */ + (0 << 5) | /* SRPR: Self-Refresh Controller Power Rail */ + (0 << 6) | /* FBPR: FB Power Rail */ + (0 << 8) | /* GPR: GPU Power Rail */ + (0 << 10) | /* GCR: GC6 ROM */ + (1 << 11) | /* PTH: No SMI Handler */ + (0 << 12) | /* NOT: Supports Notify on GC6 State done */ + (1 << 13) | /* MHYB: MS Hybrid Support */ + (0 << 14) | /* RPC: Root Port Control */ + (0 << 15) | /* GC6 Version (GC6-E) */ + (0 << 17) | /* GEI: GC6 Exit ISR Support */ + (0 << 18) | /* GSW: GC6 Self Wakeup */ + (0x200 << 20))) /* MXRV: Highest Revision */ + } + Case (JT_FUNC_POWERCONTROL) + { + CreateField (Arg1, 0, 3, GPC) /* GPU Power Control */ + CreateField (Arg1, 4, 1, PPC) /* Panel Power Control */ + CreateField (Arg1, 14, 2, DFGC) /* Defer GC6 enter/exit */ + CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */ + + If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0) + { + DFEN = ToInteger(DFGC) + DFCI = ToInteger(GPC) + DFCO = ToInteger(GPCX) + } + + Local0 = Buffer (4) { 0x0 } + CreateField (Local0, 0, 3, CGCS) /* Current GC State */ + CreateField (Local0, 3, 1, CGPS) /* Current GPU power status */ + CreateField (Local0, 7, 1, CPSS) /* Current panel and SRC state */ + + /* Leave early if deferred GC6 is requested */ + If (DFEN != 0) + { + CGCS = 1 + CGPS = 1 + Return (Local0) + } + + Switch (ToInteger(GPC)) + { + /* Get GCU GCx Sleep Status */ + Case (NVJT_GPC_GSS) + { + If (GC6E == GC6_STATE_ENTERED) + { + /* GC6 */ + CGPS = 1 + CGCS = 1 + } + Else + { + CGPS = 0 + CGCS = 3 + } + } + Case (NVJT_GPC_EGNS) + { + /* Enter GC6; no self-refresh */ + GC6I() + CPSS = 1 + } + Case (NVJT_GPC_EGIS) + { + /* Enter GC6; enable self-refresh */ + GC6I() + If (ToInteger (PPC) == 0) + { + CPSS = 0 + } + } + Case (NVJT_GPS_XGXS) + { + /* Exit GC6; stop self-refresh */ + GC6O() + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + Case (NVJT_GPS_XGIS) + { + /* Exit GC6 for self-refresh */ + GC6O() + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + } + + Return (Local0) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/google/brya/acpi/nvop.asl b/src/mainboard/google/brya/acpi/nvop.asl new file mode 100644 index 0000000..cd1bdbd --- /dev/null +++ b/src/mainboard/google/brya/acpi/nvop.asl @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NVOP_FUNC_SUPPORT 0x00 +#define NVOP_FUNC_GET_OBJ_BY_TYPE 0x10 +#define NVOP_FUNC_OPTIMUS_CAPS 0x1a +#define NVOP_FUNC_OPTIMUS_STATUS 0x1b + +Method (NVOP, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (NVOP_FUNC_SUPPORT) + { + Return (ITOB( + (1 << NVOP_FUNC_SUPPORT) | + (1 << NVOP_FUNC_OPTIMUS_CAPS) | + (1 << NVOP_FUNC_OPTIMUS_STATUS))) + } + Case (NVOP_FUNC_OPTIMUS_CAPS) + { + CreateField(Arg1, 0, 1, FLUP) /* Flag Update */ + CreateField(Arg1, 1, 1, CSOT) /* Change configuration Space Owner Target */ + CreateField(Arg1, 2, 1, CSOW) /* Change configuration Space Owner Write */ + CreateField(Arg1, 24, 2, NPCE) /* New Power Control Enable setting */ + + /* Change Optimus power control capabilities */ + If (ToInteger(FLUP) != 0 && ToInteger(NPCE) != 0) + { + OPCS = NPCE + } + + /* Change PCI configuration space save/restore owner */ + If (ToInteger(CSOW) == 1) + { + PCIO = CSOT + } + + /* Current GPU Control Status */ + If (\_SB.PCI0.PEG1.PGPR._STA == 1) + { + Local0 = 3 + } + Else + { + Local0 = 0 + } + + Return (ITOB( + (1 << 0) | /* Optimus Enabled */ + (Local0 << 3) | /* Current GPU Control Status */ + (0 << 6) | /* Shared Discrete GPU Hotplug Capabilities */ + (0 << 7) | /* MUXed DDC/Aux Capabilities */ + (PCIO << 8) | /* PCIe Configuration Space Owner */ + (1 << 24) | /* Platform Optimus Power Capabilities */ + (0 << 27))) /* Optimus HD Audio Codec Capabilities */ + } + Case (NVOP_FUNC_OPTIMUS_STATUS) + { + Return (ITOB( + (0 << 0) | /* Optimus Audio Codec Control */ + (0 << 2) | /* Request GPU Power State */ + (0 << 4) | /* Evaluate Requested GPU Power State */ + (0 << 5) | /* Request Optimus Adapter Policy */ + (0 << 7))) /* Evaluate Requested Optimus Adapter Selection */ + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/google/brya/acpi/peg.asl b/src/mainboard/google/brya/acpi/peg.asl new file mode 100644 index 0000000..e6c4d73 --- /dev/null +++ b/src/mainboard/google/brya/acpi/peg.asl @@ -0,0 +1,93 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +External (\_SB.PCI0.DGPU, DeviceObj) + +OperationRegion (PCIC, PCI_Config, 0x00, 0xff) +Field (PCIC, AnyAcc, NoLock, Preserve) +{ + Offset (0x52), + , 13, + LASX, 1, /* Link Active Status */ + Offset (0xe0), + , 7, + NCB7, 1, /* Scratch bit to save L2/3 state */ + Offset (0xe2), + , 2, + L23E, 1, /* L23_Rdy Entry request */ + L23R, 1 /* L23_Rdy Detect Transition */ +} + +/* L2/3 Entry sequence */ +Method (DL23, 0, Serialized) +{ + L23E = 1 + Local0 = 8 + While (Local0 > 0) + { + If (!L23E) + { + Break + } + + Sleep (16) + Local0-- + } + NCB7 = 1 +} + +/* L2/3 exit seqeuence */ +Method (LD23, 0, Serialized) +{ + If (!NCB7) + { + Return + } + + L23R = 1 + Local0 = 20 + While (Local0 > 0) + { + If (!L23R) + { + Break + } + + Sleep (16) + Local0-- + } + + NCB7 = 0 + Local0 = 8 + While (Local0 > 0) + { + If (LASX == 1) + { + Break + } + + Sleep (16) + Local0-- + } +} + +/* PEG Power Resource */ +PowerResource (PGPR, 0, 0) +{ + Method (_ON, 0, Serialized) + { + /* Power up GPU from GCOFF (or GC6 exit if deferred) */ + \_SB.PCI0.PEG1.PEGP._ON() + _STA = 1 + } + Method (_OFF, 0, Serialized) + { + /* Power down GPU to GCOFF (or GC6 entry if deferred) */ + _STA = 0 + \_SB.PCI0.PEG1.PEGP._ON() + } + Name (_STA, 0) +} + +Name (_PR0, Package() { PGPR }) +Name (_PR2, Package() { PGPR }) +Name (_PR3, Package() { PGPR }) diff --git a/src/mainboard/google/brya/acpi/power.asl b/src/mainboard/google/brya/acpi/power.asl new file mode 100644 index 0000000..cd36e80 --- /dev/null +++ b/src/mainboard/google/brya/acpi/power.asl @@ -0,0 +1,304 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* Misc. power sequencing GPU signals */ +#define GPIO_GPU_PERST_L 3 /* GPP_B3 */ +#define GPIO_GPU_NVVDD_EN 59 /* GPP_A17 */ +#define GPIO_GPU_ALLRAILS_PG 355 /* GPP_E5 */ + +/* Voltage rail control signals */ +#define GPIO_1V8_PWR_EN 368 /* GPP_E18 */ +#define GPIO_1V8_PG 370 /* GPP_E20 */ +#define GPIO_NV33_PWR_EN 63 /* GPP_A21 */ +#define GPIO_NV33_PG 64 /* GPP_A22 */ +#define GPIO_NVVDD_PWR_EN 350 /* GPP_E0 */ +#define GPIO_NVVDD_PG 366 /* GPP_E16 */ +#define GPIO_PEXVDD_PWR_EN 360 /* GPP_E10 */ +#define GPIO_PEXVDD_PG 367 /* GPP_E17 */ +#define GPIO_FBVDD_PWR_EN 61 /* GPP_A19 */ +#define GPIO_FBVDD_PG 354 /* GPP_E4 */ + +#define GC6_DEFER_TYPE_EXIT_GC6 3 + +/* Optimus Power Control State */ +Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE) + +/* PCI configuration space Owner */ +Name (PCIO, PCI_OWNER_SBIOS) + +/* Saved PCI configuration space memory (VGA Buffer) */ +Name (VGAB, Buffer (0xfb) { 0x00 }) + +/* Deferred GPU State */ +Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0) + +/* GC6 Entry/Exit state */ +Name (GC6E, GC6_STATE_EXITED) + +/* Defer GC6 entry / exit until D3-cold request */ +Name (DFEN, 0) +/* Deferred GC6 Enter control */ +Name (DFCI, 0) +/* Deferred GC6 Exit control */ +Name (DFCO, 0) + +/* "GC6 In", i.e. GC6 Entry Sequence */ +Method (GC6I, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Put PCIe link into L2/3 */ + \_SB.PCI0.PEG1.DL23() + + /* Assert GPU_PERST_L */ + \_SB.PCI0.STXS (GPIO_GPU_PERST_L) + + /* Deassert PG_GPU_ALLRAILS */ + \_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG) + + /* Deassert EN_PP0950_GPU_X */ + \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) + + /* Wait for de-assertion of PG_PP0950_GPU */ + GPPL (GPIO_PEXVDD_PG, 0, 20) + + /* Deassert EN_PPVAR_GPU_NVVDD */ + \_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN) + + /* Wait for de-assertion of PG_PPVAR_GPU_NVVDD */ + GPPL (GPIO_NVVDD_PG, 0, 20) + + /* Deassert EN_PCH_PPVAR_GPU_FBVDDQ */ + \_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN) + + /* Deassert EN_PP3300_GPU */ + \_SB.PCI0.CTXS (GPIO_NV33_PWR_EN) + + /* Wait for de-assertion of PG_PP3300_GPU */ + GPPL (GPIO_NV33_PG, 0, 20) + + GC6E = GC6_STATE_ENTERED +} + +/* "GC6 Out", i.e. GC6 Exit Sequence */ +Method (GC6O, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Assert EN_PP3300_GPU */ + \_SB.PCI0.STXS (GPIO_NV33_PWR_EN) + + /* Wait for assertion of PG_PP3300_GPU */ + GPPL (GPIO_NV33_PG, 1, 20) + + /* Deassert GPU_PERST_L */ + \_SB.PCI0.CTXS (GPIO_GPU_PERST_L) + + /* Put PCIe link into L0 state */ + \_SB.PCI0.PEG1.LD23() + + /* Wait for GPU to assert GPU_NVVDD_EN */ + GPPL (GPIO_GPU_NVVDD_EN, 1, 20) + + /* + * There is a 4ms window once the GPU asserts GPU_NVVDD_EN to + * perform the following: + * 1. Enable GPU_NVVDD + * 2. Enable GPU_PEX + * 3. Wait for all PG + * 4. Assert FBVDD + * At the end of the 4ms window, the GPU will deassert its + * GPIO1_GC6_FB_EN signal that is used to keep the FBVDD + * rail up during GC6. + */ + \_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN) + Stall (20) + \_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN) + GPPL (GPIO_NVVDD_PG, 1, 4) + GPPL (GPIO_PEXVDD_PG, 1, 4) + \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) + + /* Assert PG_GPU_ALLRAILS */ + \_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG) + + GC6E = GC6_STATE_EXITED +} + +/* GCOFF exit sequence */ +Method (PGON, 0, Serialized) +{ + /* Assert PERST# */ + \_SB.PCI0.CTXS (GPIO_GPU_PERST_L) + + /* Ramp up 1.8V rail */ + \_SB.PCI0.STXS (GPIO_1V8_PWR_EN) + GPPL (GPIO_1V8_PG, 1, 20) + + /* Ramp up NV33 rail */ + \_SB.PCI0.STXS (GPIO_NV33_PWR_EN) + GPPL (GPIO_NV33_PG, 1, 20) + + /* Ramp up NVVDD rail */ + \_SB.PCI0.STXS (GPIO_NVVDD_PWR_EN) + GPPL (GPIO_NVVDD_PG, 1, 5) + + /* Ramp up PEXVDD rail */ + \_SB.PCI0.STXS (GPIO_PEXVDD_PWR_EN) + GPPL (GPIO_PEXVDD_PG, 1, 5) + + /* Ramp up FBVDD rail */ + \_SB.PCI0.STXS (GPIO_FBVDD_PWR_EN) + GPPL (GPIO_FBVDD_PG, 1, 5) + + /* All rails are good */ + \_SB.PCI0.STXS (GPIO_GPU_ALLRAILS_PG) + Sleep (1) + + /* Deassert PERST# */ + \_SB.PCI0.STXS (GPIO_GPU_PERST_L) +} + +/* GCOFF entry sequence */ +Method (PGOF, 0, Serialized) +{ + /* Assert PERST# */ + \_SB.PCI0.CTXS (GPIO_GPU_PERST_L) + Sleep (5) + + /* All rails are about to go down */ + \_SB.PCI0.CTXS (GPIO_GPU_ALLRAILS_PG) + + /* Ramp down FBVDD */ + \_SB.PCI0.CTXS (GPIO_FBVDD_PWR_EN) + GPPL (GPIO_FBVDD_PG, 0, 20) + + /* Ramp down PEXVDD */ + \_SB.PCI0.CTXS (GPIO_PEXVDD_PWR_EN) + GPPL (GPIO_PEXVDD_PG, 0, 20) + + /* Ramp down NVVDD */ + \_SB.PCI0.CTXS (GPIO_NVVDD_PWR_EN) + GPPL (GPIO_NVVDD_PG, 0, 20) + + /* Ramp down NV33 */ + \_SB.PCI0.CTXS (GPIO_NV33_PWR_EN) + GPPL (GPIO_NV33_PG, 0, 20) + + /* Ramp down 1.8V */ + \_SB.PCI0.CTXS (GPIO_1V8_PWR_EN) + GPPL (GPIO_1V8_PG, 0, 20) +} + +/* Handle deferred GC6 vs. poweron request */ +Method (NPON, 0, Serialized) +{ + If (DFEN == GC6_DEFER_ENABLE) /* 1 */ + { + If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) /* 3 */ + { + GC6O() + } + + DFEN = GC6_DEFER_DISABLE + } + Else + { + PGON() + } +} + +/* Handle deferred GC6 vs. poweroff request */ +Method (NPOF, 0, Serialized) +{ + If (DFEN == GC6_DEFER_ENABLE) + { + /* Deferred GC6 entry */ + If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS) + { + GC6I() + } + + DFEN = GC6_DEFER_DISABLE + } + Else + { + PGOF() + } +} + + + +Method (_ON, 0, Serialized) +{ + PGON() +} + +Method (_OFF, 0, Serialized) +{ + PGOF() +} + +/* Put device into D0 */ +Method (_PS0, 0, NotSerialized) +{ + If (OPS0 == OPTIMUS_CONTROL_RUN_PS0) + { + /* Restore PCI config space */ + If (PCIO == PCI_OWNER_SBIOS) + { + Local0 = VGAR + CreateField(Local0, 40, 2008, VGAS) /* VGA Registers to Save */ + VGAS = VGAB + VGAR = Local0 + } + + /* Poweron or deferred GC6 exit */ + NPON() + + OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0 + } +} + +/* Put device into D3 */ +Method (_PS3, 0, NotSerialized) +{ + If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE) + { + /* Save PCI config space to ACPI buffer */ + If (PCIO == PCI_OWNER_SBIOS) + { + Local0 = VGAR + CreateField(Local0, 40, 2008, VGAS) /* VGA Registers to Save */ + VGAB = VGAS + } + + /* Poweroff or deferred GC6 entry */ + NPOF() + + /* Because _PS3 ran _OFF, _PS0 must run _ON */ + OPS0 = OPTIMUS_CONTROL_RUN_PS0 + + /* OPCS is one-shot, so reset it */ + OPCS = OPTIMUS_POWER_CONTROL_DISABLE + } +} + +/* + * Normally, _ON and _OFF of the power resources listed in _PRx will be + * evaluated before entering D0/D3. However, for Optimus, the package + * should refer to the PCIe controller itself, not a dependent device. + */ +Name (_PR0, Package() { \_SB.PCI0.PEG1 }) +Name (_PR3, Package() { \_SB.PCI0.PEG1 }) + +Method (_STA, 0, Serialized) +{ + If (GC6E == GC6_STATE_EXITED && + \_SB.PCI0.GTXS(GPIO_GPU_ALLRAILS_PG) == 1) + { + Return (0xF) + } + Else + { + Return (0) + } +} diff --git a/src/mainboard/google/brya/acpi/utility.asl b/src/mainboard/google/brya/acpi/utility.asl new file mode 100644 index 0000000..4fc03e8 --- /dev/null +++ b/src/mainboard/google/brya/acpi/utility.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Poll a GPIO until it goes to the specified state + * Arg0 == GPIO # + * Arg1 == state (0 or 1) + * Arg2 == timeout in ms + */ +Method (GPPL, 3, Serialized) +{ + Local0 = GRXS (Arg0) + Local7 = Arg2 * 10000 + Local7 = Timer + Local7 + While (Local0 != Arg1 && Timer < Local7) + { + Stall (10) + Local0 = \_SB.PCI0.GRXS (Arg0) + } +} + +/* Convert from 32-bit integer to 4-byte buffer (little-endian) */ +Method (ITOB, 1) +{ + Local0 = Buffer(4) { 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Return (Local0) +} diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl index 82cafcf..f86b289 100644 --- a/src/mainboard/google/brya/dsdt.asl +++ b/src/mainboard/google/brya/dsdt.asl @@ -44,4 +44,8 @@ /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl> } + +#if CONFIG(INCLUDE_NVIDIA_GPU_ASL) + #include "acpi/gpu_top.asl" +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/62931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifce1610210e9636e87dda4b55c8287334adfcc42 Gerrit-Change-Number: 62931 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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