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Change subject: mb/google/brya/var/agah: Add GPU power sequencing
......................................................................
mb/google/brya/var/agah: Add GPU power sequencing
This patch adds support for power sequencing of the Nvidia GN3050 for
agah, which uses PCH GPIOs to control the 5 power rails required for
the GPU. The GPU is power sequenced on during mainboard
initialization, then it is enumerated on the PCI bus and its resources
are assigned. This GPU will be used in a sort of "hybrid graphics"
mode, therefore during finalization, since its PCI BARs are saved into
ACPI memory and the GPU is not required upon initial boot, the GPU is
power sequenced off.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I1072be12ef58af5859e2a2d19c4a9c1adc0b0f88
---
M src/mainboard/google/brya/variants/agah/Makefile.inc
M src/mainboard/google/brya/variants/agah/overridetree.cb
A src/mainboard/google/brya/variants/agah/variant.c
3 files changed, 190 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62384/2
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Change subject: mb/google/brya/var/agah: Fix GPU GPIOs
......................................................................
mb/google/brya/var/agah: Fix GPU GPIOs
While adding this train of patches to program the dGPU power sequences,
I noticed some of the GPU GPIOs are incorrectly programmed in ramstage,
so this patch fixes the settings.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: I622b1f5cfba84727bb31792358ca4162c7fa9f52
---
M src/mainboard/google/brya/variants/agah/gpio.c
1 file changed, 7 insertions(+), 7 deletions(-)
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Change subject: mb/google/brya: Add variant_init and variant_finalize callbacks
......................................................................
mb/google/brya: Add variant_init and variant_finalize callbacks
Some brya variants may need to initialize and finalize some
variant-specific devices during ramstage, therefore add the
commonly-used hooks and callbacks to support this.
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Change-Id: Iede6dc5a5b9a7385fedd59d4eeaaba118eff0e20
---
M src/mainboard/google/brya/mainboard.c
M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h
2 files changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/62382/2
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 7:
(3 comments)
File src/soc/intel/common/block/usb4/usb4.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144294):
https://review.coreboot.org/c/coreboot/+/62723/comment/9b4b6828_c7428764
PS7, Line 32: const struct soc_intel_common_config *config = chip_get_common_soc_structure();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144294):
https://review.coreboot.org/c/coreboot/+/62723/comment/00167b6c_f70dbf5a
PS7, Line 32: const struct soc_intel_common_config *config = chip_get_common_soc_structure();
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144294):
https://review.coreboot.org/c/coreboot/+/62723/comment/d9ccedaa_c89499c0
PS7, Line 34: if(!config->tcss_ops.valid_tbt_auth())
space required before the open parenthesis '('
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
soc/intel/common: Configure TCSS access through IOE P2SB
This change abstracts the TCSS access through IOE P2SB on Meteor Lake.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/cfg.h
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/Kconfig
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params.c
9 files changed, 52 insertions(+), 37 deletions(-)
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
soc/intel/common: Configure TCSS access through IOE P2SB
This change abstracts the TCSS access through IOE P2SB on Meteor Lake.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/cfg.h
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/Kconfig
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params.c
9 files changed, 52 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62723/7
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Change subject: util/spd_tools: Add support for exclusive IDs
......................................................................
util/spd_tools: Add support for exclusive IDs
Currently memory parts that use the same SPD are assigned the same ID by
spd_tools. This commit adds support for exclusive IDs. When given an
exclusive ID a memory part will not share its ID with other parts unless
they have also have the same exclusive ID.
BUG=b:225161910
TEST=Ran part_id_gen and checked that exclusive IDs work correctly and
that the current behavior still works in their abscence.
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: Ife5afe32337f69bc06451ce16238c7a83bc983c8
---
M util/spd_tools/README.md
M util/spd_tools/src/part_id_gen/part_id_gen.go
2 files changed, 70 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62905/6
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Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
Patch Set 6:
(11 comments)
File src/soc/intel/alderlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/882315de_6af7a93d
PS6, Line 854: config->common_soc_config.tcss_ops.valid_tbt_auth = tcss_valid_tbt_auth;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/ce50fa01_5f3f593b
PS6, Line 854: config->common_soc_config.tcss_ops.valid_tbt_auth = tcss_valid_tbt_auth;
please, no spaces at the start of a line
File src/soc/intel/common/block/include/intelblocks/tcss.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/1ef33b05_056b2390
PS6, Line 141: void (*configure_aux_bias_pads)(const struct typec_aux_bias_pads *pads);
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/181e3814_b67305ac
PS6, Line 141: void (*configure_aux_bias_pads)(const struct typec_aux_bias_pads *pads);
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/5f5c9945_3174c14c
PS6, Line 142: bool (*valid_tbt_auth)(void);
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/5aa4690e_1fa1b2b8
PS6, Line 142: bool (*valid_tbt_auth)(void);
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/fcc7de4d_43bc83a3
PS6, Line 155: const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]);
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/18d396d1_bd142ca7
PS6, Line 155: const struct typec_aux_bias_pads aux_bias_pads[MAX_TYPE_C_PORTS]);
please, no spaces at the start of a line
File src/soc/intel/common/block/usb4/usb4.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/7bab1333_d331f1a0
PS6, Line 32: const struct soc_intel_common_config *config = chip_get_common_soc_structure();
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/096e0f55_5849f7c8
PS6, Line 32: const struct soc_intel_common_config *config = chip_get_common_soc_structure();
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144291):
https://review.coreboot.org/c/coreboot/+/62723/comment/096d5004_af1ceb9e
PS6, Line 34: if(!config->tcss_ops.valid_tbt_auth())
space required before the open parenthesis '('
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: soc/intel/common: Configure TCSS access through IOE P2SB
......................................................................
soc/intel/common: Configure TCSS access through IOE P2SB
This change abstracts the TCSS access through IOE P2SB on Meteor Lake.
BUG=b:213574324
TEST=Build platforms coreboot images successfully.
Change-Id: I3302aabfb5f540c41da6359f11376b4202c6310b
Signed-off-by: John Zhao <john.zhao(a)intel.com>
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/cfg.h
M src/soc/intel/common/block/include/intelblocks/tcss.h
M src/soc/intel/common/block/tcss/Kconfig
M src/soc/intel/common/block/tcss/tcss.c
M src/soc/intel/common/block/usb4/usb4.c
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params.c
9 files changed, 52 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/62723/6
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Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62889 )
Change subject: soc/intel/apollolake: Correct enum for PrimaryVideoAdaptor FSP parameter
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/apollolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/62889/comment/51f24a68_bdabb24a
PS2, Line 236: GPU_PRIMARY_PCI
> I will have access to an Intel CRB in two weeks and will test to be sure.
Sounds great! Thanks
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