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Change subject: mb/google/brya/variants/crota: set up gpio
......................................................................
Patch Set 8:
(2 comments)
File src/mainboard/google/brya/variants/crota/gpio.c:
https://review.coreboot.org/c/coreboot/+/62854/comment/4f01ddfa_f5d15426
PS7, Line 49: /* E22 : DDPA_CTRLCLK ==> USB_C0_AUX_DC_STRAP_P */
: PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6),
> Is this supposed to be an AUX DC bias GPIO?
Yes, we found this pin set DY in PCB, so we set NC for this pin.
https://review.coreboot.org/c/coreboot/+/62854/comment/a07c5064_32fb5aa8
PS7, Line 143: /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN (set here for correct power sequencing) */
: PAD_CFG_GPO(GPP_A12, 1, DEEP),
> is this the 850-GL ? please follow redrix for guidelines implementing the WWAN power sequencing
Yes, we follow redrix for the WWAN power sequencing. Thanks.
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Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
......................................................................
Removed Code-Review+2 by Peichao Wang <pwang12(a)lenovo.corp-partner.google.com>
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Change subject: mb/google/dedede/var/beadrix: Enable LTE function by FW_CONFIG option
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/google/dedede/variants/beadrix/gpio.c:
https://review.coreboot.org/c/coreboot/+/62801/comment/88291de2_abd4a666
PS1, Line 91: BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);
> Honestly, it's a little bit of cargo culting at this point... […]
So currently I will not modify this CL.
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Change subject: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
......................................................................
Patch Set 5:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62918/comment/5833ef5c_19938727
PS4, Line 7: L1 entry
> `L1 max entry delay`
Update in latest patch.
https://review.coreboot.org/c/coreboot/+/62918/comment/5cee5485_ba63026e
PS4, Line 10: eMMC can not detect issue.
> Add something like: […]
Update in latest patch.
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Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
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Patch Set 9: Code-Review+2
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Change subject: mb/google/brya/var/taeko: Enable Genesys L1 entry delay
......................................................................
Patch Set 4: Code-Review+2
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Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
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Patch Set 4: Code-Review+2
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Change subject: mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62952/comment/f8d0d49c_fb3c9a41
PS1, Line 7: /mb/google/brya/var/taniks: Modify DPTF setting for taniks
> Please write something like: […]
Done
https://review.coreboot.org/c/coreboot/+/62952/comment/2c087786_4343c904
PS1, Line 7: /
> please remove leading slash
Done
https://review.coreboot.org/c/coreboot/+/62952/comment/d3877185_401e285c
PS1, Line 12: TEST=build and tested on taniks board
> Tested how? Just booted or ran some benchmark?
Updated test method.
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Hello build bot (Jenkins), YH Lin, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62952
to look at the new patch set (#3).
Change subject: mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C
......................................................................
mb/google/brya/var/taniks: Increase TSR2 threshold from 40 °C to 70 °C
Change settings according to thermal team test results
BUG=b:215033682
TEST=build and tested fan works normally on taniks
Change-Id: I567815782ece4ab7fcec7da6b787ee9eec27aba4
Signed-off-by: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/taniks/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62952/3
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