coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
by Peichao Wang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang, Kane Chen, Tim Wawrzynczak. Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config. ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 13 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:54:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Kevin Chang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62973/comment/5abb84f0_f873c750 PS1, Line 9: that disables L0s at root port. > `, so disable L0s at the root port` Updated in latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 2 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
by Kevin Chang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kane Chen, Tim Wawrzynczak. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config. ...................................................................... Patch Set 13: (3 comments) File src/soc/intel/alderlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/62919/comment/a0f405a6_a90123a3 PS11, Line 300: static unsigned int get_aspm_control(enum ASPM_control ctl) > nit: can you add a comment similar to the one above get_l1_substate_control() […] Updated in latest patch. File src/soc/intel/common/block/include/intelblocks/pcie_rp.h: https://review.coreboot.org/c/coreboot/+/62919/comment/9ea09bf9_ee28f025 PS11, Line 63: ntrol PcieRpL1Substates; : > `/* PCIe RP ASPM */` Updated in latest patch. https://review.coreboot.org/c/coreboot/+/62919/comment/b3d4bd0b_f35741b0 PS11, Line 65: PcieRpAspm > nit: […] Updated in latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 13 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:49:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
by Martin L Roth (Code Review) 22 Mar '22

22 Mar '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62918 ) Change subject: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay ...................................................................... mb/google/brya/var/taeko: Enable Genesys L1 max entry delay The workaround causes the eMMC controller to not enter its L1 during the boot process BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62918 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin L Roth <martinroth(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig.name 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Peichao Wang: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index dd7935c..f1cab9d 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -136,6 +136,7 @@ select DRIVERS_GENERIC_BAYHUB_LV2 select DRIVERS_GENESYSLOGIC_GL9750 select DRIVERS_GENESYSLOGIC_GL9763E + select DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX if DRIVERS_GENESYSLOGIC_GL9763E select CHROMEOS_WIFI_SAR if CHROMEOS config BOARD_GOOGLE_TAEKO4ES -- To view, visit https://review.coreboot.org/c/coreboot/+/62918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Gerrit-Change-Number: 62918 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
by Martin L Roth (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62918 ) Change subject: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Gerrit-Change-Number: 62918 Gerrit-PatchSet: 5 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:46:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
by Martin L Roth (Code Review) 22 Mar '22

22 Mar '22

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62917 ) Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E ...................................................................... drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E Add an option to set L1 entry delay to Max for GL9763E. The L1 entry delay will be changed to expected value by sdhci-pci-gli driver in Linux v5.14. BUG=b:220079865 TEST=build and verify the value of GL9763E's 0x8A4[28:19] register is 0x3FF. Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Signed-off-by: Ben Chuang <benchuanggli(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62917 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Martin L Roth <martinroth(a)google.com> --- M src/drivers/genesyslogic/gl9763e/Kconfig M src/drivers/genesyslogic/gl9763e/gl9763e.c M src/drivers/genesyslogic/gl9763e/gl9763e.h 3 files changed, 13 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Peichao Wang: Looks good to me, approved Subrata Banik: Looks good to me, but someone else must approve diff --git a/src/drivers/genesyslogic/gl9763e/Kconfig b/src/drivers/genesyslogic/gl9763e/Kconfig index c254707..555ad91 100644 --- a/src/drivers/genesyslogic/gl9763e/Kconfig +++ b/src/drivers/genesyslogic/gl9763e/Kconfig @@ -1,2 +1,8 @@ config DRIVERS_GENESYSLOGIC_GL9763E - bool + bool "Genesys Logic GL9763E" + default n + +config DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX + bool "Set L1 entry delay to MAX" + depends on DRIVERS_GENESYSLOGIC_GL9763E + default n diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.c b/src/drivers/genesyslogic/gl9763e/gl9763e.c index 4dcfbdc..a4842e8 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.c +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.c @@ -23,6 +23,11 @@ pci_or_config32(dev, SCR, SCR_AXI_REQ); /* Disable L0s support */ pci_and_config32(dev, CFG_REG_2, ~CFG_REG_2_L0S); + + if (CONFIG(DRIVERS_GENESYSLOGIC_GL9763E_L1_MAX)) + /* Set L1 entry delay to MAX */ + pci_or_config32(dev, CFG_REG_2, CFG_REG_2_L1DLY_MAX); + /* Set SSC to 30000 ppm */ pci_update_config32(dev, PLL_CTL_2, ~PLL_CTL_2_MAX_SSC_MASK, MAX_SSC_30000PPM); /* Enable SSC */ diff --git a/src/drivers/genesyslogic/gl9763e/gl9763e.h b/src/drivers/genesyslogic/gl9763e/gl9763e.h index 7f5dbf9..647920c 100644 --- a/src/drivers/genesyslogic/gl9763e/gl9763e.h +++ b/src/drivers/genesyslogic/gl9763e/gl9763e.h @@ -14,6 +14,7 @@ #define CFG_REG_2 0x8A4 #define CFG_REG_2_L0S BIT(11) +#define CFG_REG_2_L1DLY_MAX (0x3FF << 19) #define PLL_CTL 0x938 #define PLL_CTL_SSC BIT(19) -- To view, visit https://review.coreboot.org/c/coreboot/+/62917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Gerrit-Change-Number: 62917 Gerrit-PatchSet: 5 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lai Jason <jasonlai.genesyslogic(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E
by Martin L Roth (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Ben Chuang, Paul Menzel. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62917 ) Change subject: drivers/genesyslogic/gl9763e: Add set L1 entry delay to Max for GL9763E ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19d4dfb7b873d09ff30ad4d2d63b876047c21601 Gerrit-Change-Number: 62917 Gerrit-PatchSet: 4 Gerrit-Owner: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Lai Jason <jasonlai.genesyslogic(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ben Chuang <benchuanggli(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:45:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
by Peichao Wang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang, Kane Chen. Peichao Wang has removed a vote from this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config. ...................................................................... Removed Code-Review+2 by Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 11 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-MessageType: deleteVote

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Change in coreboot[master]: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Felix Singer, Jamie Ryu, Ethan Tsao, Ravishankar Sarawadi, Paul Menzel, Raj Astekar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62772 ) Change subject: soc/intel/mtl: Do initial Meteor Lake SoC commit till bootblock ...................................................................... Patch Set 6: (1 comment) Patchset: PS4: > > Any guidance/documentation on HOW-TOs for stage-wise Make build setup? Wondering when building coreboot.rom if it stubs out stages if not included. > > I have tried creating a skeleton MTL board and select MTL SoC code to allow building only the bootblock code that you have added here.But unfortunately, it's too much changes that I had to make to resolve the code dependencies to allow this bootblock code to get successfully compiled. > > I have noticed the main reasons for those compilation errors are due to inclusion of common code from SoC block, each common code block has some dependencies over other header files or the code block which is not added by this CL, hence, i had to keep on adding those, for example this CL selects `PCH_BASE` Kconfig from SoC code, now `PCH_BASE` kconfig internally selects GPIO Common code block, and GPIO common code block expects SoC code to have GPIO support. This has become circular dependencies. > > IMO, we unfortunately need to add SoC code incrementally without hooking a MB code till we have SOC code ready with `ramstage` code changes. > > Having said that, this CL need lots of rework to add only the bootblock code and corresponding header (which is not the case with this CL), so, please keep on adding those header files when you need those, rather dumping everything at once. Please check the build failure https://qa.coreboot.org/job/coreboot-gerrit/200000/testReport/junit/(root)/… -- To view, visit https://review.coreboot.org/c/coreboot/+/62772 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26479fcc3a3f9c6f8ebf5f198ab0809f0b4a2cc4 Gerrit-Change-Number: 62772 Gerrit-PatchSet: 6 Gerrit-Owner: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Ethan Tsao <ethan.tsao(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:41:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62973/comment/c720b713_ff7822f9 PS1, Line 9: that disables L0s at root port. `, so disable L0s at the root port` -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 03:41:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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