coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 18 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:44:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL
by Joey Peng (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: YH Lin, Paul Menzel, Tim Wawrzynczak. Joey Peng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62954 ) Change subject: mb/google/brya/var/taeko: Add new FW_CONFIG option for THERMAL ...................................................................... Patch Set 6: (2 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/62954/comment/506262b4_88901e8f PS3, Line 7: mb/google/brya/var/taeko:Add > Please add a space after the colon. Done https://review.coreboot.org/c/coreboot/+/62954/comment/b58c33e0_c4eedbc6 PS3, Line 9: tarlo > 1. What is tarlo? Should it be mentioned in the summary? […] 1.Tarlo is a project which uses the same fw with taeko, I have updated the commit message to prevent misunderstanding. 2. These values are provided by LCFC thermal team. Please see issue tracker for more details. -- To view, visit https://review.coreboot.org/c/coreboot/+/62954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37f79cde502115bbf65bb97216eddb6ea22b1648 Gerrit-Change-Number: 62954 Gerrit-PatchSet: 6 Gerrit-Owner: Joey Peng <joey.peng(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rasheed Hsueh <rasheed.hsueh(a)lcfc.corp-partner.google.com> Gerrit-CC: Sunshine Chao <sunshine.chao(a)lcfc.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:38:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s GL9763e doesn’t support L0s state, so disable L0s at the root port. BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Reviewed-on: https://review.coreboot.org/c/coreboot/+/62973 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Peichao Wang: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 75672ae..b4cda82 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -407,6 +407,7 @@ .clk_src = 0, .clk_req = 0, .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, }" chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: This was split from CB:62919 which has been up for review for several days, this has two +2s, and it is mainboard-specific, submitting a little early. -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:02:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
by Tim Wawrzynczak (Code Review) 22 Mar '22

22 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config ...................................................................... soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config This change provides config for devicetree to control ASPM per port BUG=b:220079865 TEST=Build FW and run stress exceed 2500 cycles on taeko. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62919 Reviewed-by: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Martin L Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 2 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Peichao Wang: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 2f3027d..4a27cb5 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -297,6 +297,26 @@ return ctl - 1; } +/* + * Chip config parameter pcie_rp_aspm uses (UPD value + 1) because + * a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure + * that the mainboard setting does not disable ASPM incorrectly, chip + * config parameter values are offset by 1 with 0 meaning use FSP UPD default. + * get_aspm_control() ensures that the right UPD value is set in fsp_params. + * 0: Use FSP UPD default + * 1: Disable ASPM + * 2: L0s only + * 3: L1 only + * 4: L0s and L1 + * 5: Auto configuration + */ +static unsigned int get_aspm_control(enum ASPM_control ctl) +{ + if ((ctl > ASPM_AUTO) || (ctl == ASPM_DEFAULT)) + ctl = ASPM_AUTO; + return ctl - 1; +} + /* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */ static uint16_t get_vccin_aux_imon_iccmax(void) { @@ -632,6 +652,8 @@ s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); + if (rp_cfg->pcie_rp_aspm) + s_cfg->PcieRpAspm[i] = get_aspm_control(rp_cfg->pcie_rp_aspm); } } diff --git a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h index 2f3b83c..66ced7e 100644 --- a/src/soc/intel/common/block/include/intelblocks/pcie_rp.h +++ b/src/soc/intel/common/block/include/intelblocks/pcie_rp.h @@ -42,6 +42,16 @@ L1_SS_L1_2, }; +/* This enum is for passing into an FSP UPD, typically ASPM */ +enum ASPM_control { + ASPM_DEFAULT, + ASPM_DISABLE, + ASPM_L0S, + ASPM_L1, + ASPM_L0S_L1, + ASPM_AUTO, +}; + /* PCIe Root Ports */ struct pcie_rp_config { /* CLKOUT_PCIE_P/N# used by this root port as per schematics. */ @@ -51,6 +61,8 @@ enum pcie_rp_flags flags; /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates; + /* PCIe RP ASPM */ + enum ASPM_control pcie_rp_aspm; }; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 18 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Eric Lai (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:01:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
by Eric Lai (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang, Kane Chen, Paul Menzel. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 17 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 04:59:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay
by 9elements QA (Code Review) 22 Mar '22

22 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62918 ) Change subject: mb/google/brya/var/taeko: Enable Genesys L1 max entry delay ...................................................................... Patch Set 6: Automatic boot test returned (PASS/FAIL/TOTAL): 11 / 1 / 12 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96489 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96488 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/96487 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/96486 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/96485 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96484 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/96483 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/96482 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96481 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/96480 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/96479 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/96478 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/62918 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I142a816611e204e6c8577d15b3f0a0e08251f848 Gerrit-Change-Number: 62918 Gerrit-PatchSet: 6 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 04:58:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
by Peichao Wang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kevin Chang, Kane Chen, Paul Menzel. Peichao Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config ...................................................................... Patch Set 17: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 17 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 04:55:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config
by Kevin Chang (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Kane Chen, Paul Menzel. Kevin Chang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62919 ) Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config ...................................................................... Patch Set 17: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62919/comment/35c2ffdc_9f8d82c4 PS16, Line 7: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config. > Please remove the dot/period at the end [1]. […] Updated in latest patch. https://review.coreboot.org/c/coreboot/+/62919/comment/d7223f45_1ccea3c3 PS16, Line 12: TEST=Build FW and run stress exceed 2500 cycles. > On what system? Updated in latest patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988 Gerrit-Change-Number: 62919 Gerrit-PatchSet: 17 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 04:50:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022