coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... soc/intel/alderlake: Log CSE RO write protection info for ADL The patch logs write protection information for Alder Lake platform. As part of write protection informaiton, coreboot logs status on CSE RO write protection and range. Also, triggers assert if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 --- M src/soc/intel/alderlake/me.c 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/1 diff --git a/src/soc/intel/alderlake/me.c b/src/soc/intel/alderlake/me.c index ea94902..ce5d3c3 100644 --- a/src/soc/intel/alderlake/me.c +++ b/src/soc/intel/alderlake/me.c @@ -1,7 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> #include <bootstate.h> #include <intelblocks/cse.h> +#include <intelblocks/spi.h> #include <console/console.h> #include <soc/me.h> #include <stdint.h> @@ -161,6 +163,21 @@ hfsts6.fields.cpu_debug_disable ? "YES" : "NO"); printk(BIOS_DEBUG, "ME: TXT Support : %s\n", hfsts6.fields.txt_support ? "YES" : "NO"); + + bool cse_ro_wp_en = is_spi_wp_cse_ro_en(); + printk(BIOS_DEBUG, "ME: WP for RO is enabled : %s\n", + cse_ro_wp_en ? "YES" : "NO"); + + if (cse_ro_wp_en) { + uint32_t base, limit; + spi_get_wp_cse_ro_range(&base, &limit); + printk(BIOS_DEBUG, "ME: RO write protection scope - Start=0x%X, End=0x%X\n", + base, limit); + } + + /* If EOM is disabled, but CSE RO is not write protected, trigger assert */ + assert(hfsts1.fields.mfg_mode || (!hfsts1.fields.mfg_mode && cse_ro_wp_en)); + } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_EXIT, print_me_fw_version, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Sridhar Siricilla (Code Review) 22 Mar '22

22 Mar '22

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62986 ) Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... soc/intel/common: Add APIs to check CSE's write protection info The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a GPRD register which is part of Descriptor Region. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b --- M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/spi/spi.c 2 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/62986/1 diff --git a/src/soc/intel/common/block/include/intelblocks/spi.h b/src/soc/intel/common/block/include/intelblocks/spi.h index 38c9a57..7997734 100644 --- a/src/soc/intel/common/block/include/intelblocks/spi.h +++ b/src/soc/intel/common/block/include/intelblocks/spi.h @@ -4,6 +4,15 @@ #define SOC_INTEL_COMMON_BLOCK_SPI_H /* + * Check if write protection for CSE RO is enabled or not. + * Returns 1 if write protection for CSE RO is enabled, 0 otherwise. + */ +bool is_spi_wp_cse_ro_en(void); + +/* Gets CSE's write protected area's base address and size */ +void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *size); + +/* * SoC overrides * * All new SoC must implement below functionality. diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 50e1bea..a753a3f 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -1,14 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#define __SIMPLE_DEVICE__ + #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/spi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> #include <intelblocks/spi.h> #include <soc/pci_devs.h> #include <spi-generic.h> +#include <device/mmio.h> const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { .ctrlr = &fast_spi_flash_ctrlr, .bus_start = 0, .bus_end = 0 }, @@ -20,6 +24,87 @@ const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); + +#define MMIO_BIOS_GPR0 0x98 + +union spi_bios_gpr0 { + struct { + /* Specified write protection is enabled */ + /* + * This field corresponds to flash address bits 26:12 + * and specifies the lower limit of protected range. + */ + uint32_t protect_range_base:15; + + /* Specifies read protection is enabled */ + uint32_t read_protect_en:1; + + /* + * This field corresponds to flash address bits 26:12 + * and specifies the upper limit of the protected range + */ + uint32_t protect_range_limit:15; + + uint32_t write_protect_en:1; + } __packed fields; + + uint32_t data; +}; + +#if ENV_RAMSTAGE + +/* Read SPI BAR 0 from PCI configuration space */ +static uintptr_t get_spi_bar(pci_devfn_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + assert(bar != 0); + /* + * Bits 31-12 are the base address as per EDS for SPI, + * Don't care about 0-11 bit + */ + return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + +static uint32_t spi_read_bar(pci_devfn_t dev, uint32_t offset) +{ + return read32p(get_spi_bar(dev) + offset); +} + +static uint32_t spi_read_bios_gpr0(void) +{ + return spi_read_bar(PCH_DEV_SPI, MMIO_BIOS_GPR0); +} + +static uint32_t spi_get_wp_cse_ro_start_offset(union spi_bios_gpr0 bios_gpr0) +{ + return bios_gpr0.fields.protect_range_base << 12; +} + +static uint32_t spi_get_wp_cse_ro_limit(union spi_bios_gpr0 bios_gpr0) +{ + return bios_gpr0.fields.protect_range_limit << 12 | 0xfff; +} + +bool is_spi_wp_cse_ro_en(void) +{ + union spi_bios_gpr0 bios_gpr0; + + bios_gpr0.data = spi_read_bios_gpr0(); + return !!bios_gpr0.fields.write_protect_en; +} + +void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *limit) +{ + union spi_bios_gpr0 bios_gpr0; + + bios_gpr0.data = spi_read_bios_gpr0(); + *base = spi_get_wp_cse_ro_start_offset(bios_gpr0); + *limit = spi_get_wp_cse_ro_limit(bios_gpr0); +} +#endif + static int spi_dev_to_bus(struct device *dev) { return spi_soc_devfn_to_bus(dev->path.pci.devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Replace EDK2 code
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62985 ) Change subject: soc/intel/denverton_ns: Replace EDK2 code ...................................................................... soc/intel/denverton_ns: Replace EDK2 code Replace LShiftU64 and RShiftU64 as the defined marcro conflicats with UDK2017 headers. Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/include/soc/gpio_dnv.h 2 files changed, 13 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/62985/1 diff --git a/src/soc/intel/denverton_ns/gpio_dnv.c b/src/soc/intel/denverton_ns/gpio_dnv.c index 70138d3..03dab18 100644 --- a/src/soc/intel/denverton_ns/gpio_dnv.c +++ b/src/soc/intel/denverton_ns/gpio_dnv.c @@ -425,24 +425,19 @@ // // Update value to be programmed in HOSTSW_OWN register // - HostSoftOwnRegMask[GroupIndex] |= LShiftU64( - (uint64_t)GpioData->GpioConfig.HostSoftPadOwn & 0x1, - PadNumber); - HostSoftOwnReg[GroupIndex] |= LShiftU64( - (uint64_t)GpioData->GpioConfig.HostSoftPadOwn >> 0x1, - PadNumber); + HostSoftOwnRegMask[GroupIndex] |= + ((uint64_t)GpioData->GpioConfig.HostSoftPadOwn & 0x1) << PadNumber; + HostSoftOwnReg[GroupIndex] |= + ((uint64_t)GpioData->GpioConfig.HostSoftPadOwn >> 0x1) << PadNumber; // // Update value to be programmed in GPI_GPE_EN register // - GpiGpeEnRegMask[GroupIndex] |= LShiftU64( - (uint64_t)(GpioData->GpioConfig.InterruptConfig & 0x1), - PadNumber); - GpiGpeEnReg[GroupIndex] |= LShiftU64( - (uint64_t)(GpioData->GpioConfig.InterruptConfig & - GpioIntSci) >> - 3, - PadNumber); + GpiGpeEnRegMask[GroupIndex] |= + ((uint64_t)(GpioData->GpioConfig.InterruptConfig & 0x1) << PadNumber; + GpiGpeEnReg[GroupIndex] |= + ((uint64_t)(GpioData->GpioConfig.InterruptConfig & GpioIntSci) >> 3) + << PadNumber; } for (Index = 0; Index < NumberOfGroups; Index++) { @@ -463,10 +458,8 @@ GpioGroupInfo[Index].Community, GpioGroupInfo[Index].HostOwnOffset + 0x4), - ~(uint32_t)(RShiftU64(HostSoftOwnRegMask[Index], - 32)), - (uint32_t)( - RShiftU64(HostSoftOwnReg[Index], 32))); + ~(uint32_t)(HostSoftOwnRegMask[Index] >> 32)), + (uint32_t)(HostSoftOwnReg[Index] >> 32)); } // @@ -486,9 +479,8 @@ GpioGroupInfo[Index].Community, GpioGroupInfo[Index].GpiGpeEnOffset + 0x4), - ~(uint32_t)( - RShiftU64(GpiGpeEnRegMask[Index], 32)), - (uint32_t)(RShiftU64(GpiGpeEnReg[Index], 32))); + ~(uint32_t)(GpiGpeEnRegMask[Index] >> 32), + (uint32_t)(GpiGpeEnReg[Index] >> 32)); } } } diff --git a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h index 447064d..06a0721 100644 --- a/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h +++ b/src/soc/intel/denverton_ns/include/soc/gpio_dnv.h @@ -3,9 +3,6 @@ #ifndef _DENVERTON_NS_GPIO_H_ #define _DENVERTON_NS_GPIO_H_ -#define RShiftU64(Operand, Count) (Operand >> Count) -#define LShiftU64(Operand, Count) (Operand << Count) - #include <soc/gpio_defs.h> #ifndef __ACPI__ -- To view, visit https://review.coreboot.org/c/coreboot/+/62985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Gerrit-Change-Number: 62985 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: sc7280: Limit SPI-NOR size
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Hello Sajida Bhanu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/47145 to review the following change. Change subject: sc7280: Limit SPI-NOR size ...................................................................... sc7280: Limit SPI-NOR size Limit SPI-NOR size to 8MB. Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Signed-off-by: Shaik Sajida Bhanu <sbhanu(a)codeaurora.org> --- M src/drivers/spi/stmicro.c M src/mainboard/google/herobrine/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/47145/1 diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index 4cd8c1b..b02edf6 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -189,7 +189,7 @@ { /* N25Q256..1E */ .id[0] = STM_ID_N25Q256__1E, - .nr_sectors_shift = 13, + .nr_sectors_shift = 11, }, }; diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig index 92f77db..b92136d 100644 --- a/src/mainboard/google/herobrine/Kconfig +++ b/src/mainboard/google/herobrine/Kconfig @@ -14,7 +14,7 @@ select RTC select SOC_QUALCOMM_SC7280 select SPI_FLASH - select SPI_FLASH_WINBOND + select SPI_FLASH_STMICRO select MAINBOARD_HAS_CHROMEOS config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/47145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I31f788b5280636aca3e7e557db3e9ee53320d50d Gerrit-Change-Number: 47145 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sajida Bhanu <sbhanu(a)codeaurora.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Eric Lai (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: Could you update the comment as well :p thanks! Will +2 after. -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:39:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Eric Lai (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:38:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: Kconfig: Select UDK2017 and see what breaks
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62984 ) Change subject: Kconfig: Select UDK2017 and see what breaks ...................................................................... Kconfig: Select UDK2017 and see what breaks Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/intel/galileo/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62984/1 diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index dbe165c..5f6f065 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -10,7 +10,7 @@ select SOC_INTEL_QUARK select MAINBOARD_HAS_I2C_TPM_ATMEL select MAINBOARD_HAS_TPM2 - select UDK_2015_BINDING + select UDK_2017_BINDING config MAINBOARD_DIR diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 8cf0754..a1cd788 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -44,7 +44,7 @@ select TSC_MONOTONIC_TIMER select TSC_SYNC_MFENCE select UDELAY_TSC - select UDK_2015_BINDING + select UDK_2017_BINDING select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -- To view, visit https://review.coreboot.org/c/coreboot/+/62984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Gerrit-Change-Number: 62984 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: util/sconfig: Fix for multidomain support sconfig/devicetree.cb
by Paul Menzel (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Furquan Shaikh, Martin L Roth, Mariusz Szafrański, Jonathan Zhang, Angel Pons, Michal Motyl. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/51180 ) Change subject: util/sconfig: Fix for multidomain support sconfig/devicetree.cb ...................................................................... Patch Set 3: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/51180/comment/bf31eda2_2c3425e6 PS3, Line 11: i.e. Please adda blank line below. https://review.coreboot.org/c/coreboot/+/51180/comment/0dccf443_e8bf371c PS3, Line 20: Two domains (each with it`s own root PCI bus) and device with 00.0 Please add a blank line above. https://review.coreboot.org/c/coreboot/+/51180/comment/4a6033b5_3e746c48 PS3, Line 20: it`s its https://review.coreboot.org/c/coreboot/+/51180/comment/894192e8_3a39ae2f PS3, Line 22: Tested how? -- To view, visit https://review.coreboot.org/c/coreboot/+/51180 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd639d0cb3ed1a49ed7c7b1c77ac747ba6f77672 Gerrit-Change-Number: 51180 Gerrit-PatchSet: 3 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:27:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 3: (1 comment) File src/ec/google/chromeec/ec_dptf_helpers.c: https://review.coreboot.org/c/coreboot/+/62945/comment/017449b6_0413535b PS2, Line 134: static void write_power_pbok(const struct device *ec) > so you can ARG0 & 0x0F then store to local0. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:15:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62945 ) Change subject: ec/google: Add PSRC and PBOK method ...................................................................... Patch Set 3: (1 comment) File src/ec/google/chromeec/ec_dptf_helpers.c: https://review.coreboot.org/c/coreboot/+/62945/comment/a557e433_1acfe8a4 PS2, Line 138: cpigen_write_store(); : acpigen_emit_byte(ARG0_OP); : acpigen_emit_byte(LOCAL0_OP); : : acpigen_emit_byte(AND_OP); : acpigen_emit_byte(LOCAL0_OP); : acpigen_write_byte(0x0F); : acpigen_emit_byte(LOCAL0_OP); > yes, thanks! This is what I mean :p Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:15:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022