coreboot-gerrit March 2022

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Change in coreboot[master]: sc7280: add BL31 compilation and SDI feature support
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51519 ) Change subject: sc7280: add BL31 compilation and SDI feature support ...................................................................... Abandoned Abandon these changes as already merged: https://review.coreboot.org/c/coreboot/+/47904 -- To view, visit https://review.coreboot.org/c/coreboot/+/51519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I581eaa9c572f4db6056d5c3da177bdf868d0be7d Gerrit-Change-Number: 51519 Gerrit-PatchSet: 42 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: sc7280: Add SPI-NOR support
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47075 ) Change subject: sc7280: Add SPI-NOR support ...................................................................... sc7280: Add SPI-NOR support This implements the SPI-NOR driver for the Qualcomm QSPI core. Change-Id: I4d4159939a57648c54dcb06aea3645f1dfe10903 Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Kconfig M src/soc/qualcomm/sc7280/Makefile.inc M src/soc/qualcomm/sc7280/bootblock.c A src/soc/qualcomm/sc7280/include/soc/qspi.h A src/soc/qualcomm/sc7280/qspi.c M src/soc/qualcomm/sc7280/spi.c 6 files changed, 428 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/47075/1 diff --git a/src/soc/qualcomm/sc7280/Kconfig b/src/soc/qualcomm/sc7280/Kconfig index fc2f34b..c47ed29 100644 --- a/src/soc/qualcomm/sc7280/Kconfig +++ b/src/soc/qualcomm/sc7280/Kconfig @@ -24,4 +24,13 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK +config SC7280_QSPI + bool + default y if COMMON_CBFS_SPI_WRAPPER + prompt "Build Flash Using SPI-NOR" + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 16 + endif diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index d6f8d29..33f6def 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -6,10 +6,12 @@ bootblock-y += mmu.c bootblock-y += timer.c bootblock-y += spi.c +bootblock-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ verstage-y += timer.c verstage-y += spi.c +verstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ romstage-y += cbmem.c @@ -19,12 +21,14 @@ romstage-y += ../common/mmu.c romstage-y += mmu.c romstage-y += spi.c +romstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ ramstage-y += soc.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += spi.c +ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 807bb25..9e04351 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -2,8 +2,10 @@ #include <bootblock_common.h> #include <soc/mmu.h> +#include <soc/qspi.h> void bootblock_soc_init(void) { sc7280_mmu_init(); + quadspi_init(37500 * KHz); } diff --git a/src/soc/qualcomm/sc7280/include/soc/qspi.h b/src/soc/qualcomm/sc7280/include/soc/qspi.h new file mode 100644 index 0000000..6c40e7e --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/qspi.h @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <types.h> +#include <soc/addressmap.h> +#include <spi-generic.h> + +#ifndef __SOC_QUALCOMM_SC7280_QSPI_H__ +#define __SOC_QUALCOMM_SC7280_QSPI_H__ + +struct sc7280_qspi_regs { + u32 mstr_cfg; + u32 ahb_mstr_cfg; + u32 reserve_0; + u32 mstr_int_en; + u32 mstr_int_sts; + u32 pio_xfer_ctrl; + u32 pio_xfer_cfg; + u32 pio_xfer_sts; + u32 pio_dataout_1byte; + u32 pio_dataout_4byte; + u32 rd_fifo_cfg; + u32 rd_fifo_sts; + u32 rd_fifo_rst; + u32 reserve_1[3]; + u32 next_dma_desc_addr; + u32 current_dma_desc_addr; + u32 current_mem_addr; + u32 hw_version; + u32 rd_fifo[16]; +}; + +check_member(sc7280_qspi_regs, rd_fifo, 0x50); +static struct sc7280_qspi_regs * const sc7280_qspi = (void *) QSPI_BASE; + +// MSTR_CONFIG register + +#define TX_DATA_OE_DELAY_SHIFT 24 +#define TX_DATA_OE_DELAY_MASK (0x3 << TX_DATA_OE_DELAY_SHIFT) +#define TX_CS_N_DELAY_SHIFT 22 +#define TX_CS_N_DELAY_MASK (0x3 << TX_CS_N_DELAY_SHIFT) +#define TX_CLK_DELAY_SHIFT 20 +#define TX_CLK_DELAY_MASK (0x3 << TX_CLK_DELAY_SHIFT) +#define TX_DATA_DELAY_SHIFT 18 +#define TX_DATA_DELAY_MASK (0x3 << TX_DATA_DELAY_SHIFT) +#define LPA_BASE_SHIFT 14 +#define LPA_BASE_MASK (0xF << LPA_BASE_SHIFT) +#define SBL_EN BIT(13) +#define CHIP_SELECT_NUM BIT(12) +#define SPI_MODE_SHIFT 10 +#define SPI_MODE_MASK (0x3 << SPI_MODE_SHIFT) +#define BIG_ENDIAN_MODE BIT(9) +#define DMA_ENABLE BIT(8) +#define PIN_WPN BIT(7) +#define PIN_HOLDN BIT(6) +#define FB_CLK_EN BIT(4) +#define FULL_CYCLE_MODE BIT(3) + +// MSTR_INT_ENABLE and MSTR_INT_STATUS register + +#define DMA_CHAIN_DONE BIT(31) +#define TRANSACTION_DONE BIT(16) +#define WRITE_FIFO_OVERRUN BIT(11) +#define WRITE_FIFO_FULL BIT(10) +#define HRESP_FROM_NOC_ERR BIT(3) +#define RESP_FIFO_RDY BIT(2) +#define RESP_FIFO_NOT_EMPTY BIT(1) +#define RESP_FIFO_UNDERRUN BIT(0) + +// PIO_TRANSFER_CONFIG register + +#define TRANSFER_FRAGMENT BIT(8) +#define MULTI_IO_MODE_SHIFT 1 +#define MULTI_IO_MODE_MASK (0x7 << MULTI_IO_MODE_SHIFT) +#define TRANSFER_DIRECTION BIT(0) + +// PIO_TRANSFER_STATUS register + +#define WR_FIFO_BYTES_SHIFT 16 +#define WR_FIFO_BYTES_MASK (0xFFFF << WR_FIFO_BYTES_SHIFT) + +// RD_FIFO_CONFIG register + +#define CONTINUOUS_MODE BIT(0) + +// RD_FIFO_STATUS register + +#define FIFO_EMPTY BIT(11) +#define WR_CNTS_SHIFT 4 +#define WR_CNTS_MASK (0x7F << WR_CNTS_SHIFT) +#define RDY_64BYTE BIT(3) +#define RDY_32BYTE BIT(2) +#define RDY_16BYTE BIT(1) +#define FIFO_RDY BIT(0) + +// RD_FIFO_RESET register + +#define RESET_FIFO BIT(0) + +#define QSPI_MAX_PACKET_COUNT 0xFFC0 + +void quadspi_init(uint32_t hz); +int sc7280_claim_bus(const struct spi_slave *slave); +int sc7280_setup_bus(const struct spi_slave *slave); +void sc7280_release_bus(const struct spi_slave *slave); +int sc7280_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +int sc7280_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes); +#endif /* __SOC_QUALCOMM_SC7280_QSPI_H__ */ diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c new file mode 100644 index 0000000..a6837bc --- /dev/null +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -0,0 +1,296 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <spi-generic.h> +#include <spi_flash.h> +#include <arch/cache.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/qspi.h> +#include <soc/gpio.h> +#include <soc/clock.h> +#include <symbols.h> +#include <assert.h> +#include <gpio.h> +#include <string.h> + +#define CACHE_LINE_SIZE 64 + +static int curr_desc_idx = -1; + +struct cmd_desc { + uint32_t data_address; + uint32_t next_descriptor; + uint32_t direction:1; + uint32_t multi_io_mode:3; + uint32_t reserved1:4; + uint32_t fragment:1; + uint32_t reserved2:7; + uint32_t length:16; + //------------------------// + uint32_t bounce_src; + uint32_t bounce_dst; + uint32_t bounce_length; + uint64_t padding[5]; +}; + +enum qspi_mode { + SDR_1BIT = 1, + SDR_2BIT = 2, + SDR_4BIT = 3, + DDR_1BIT = 5, + DDR_2BIT = 6, + DDR_4BIT = 7, +}; + +enum cs_state { + CS_DEASSERT, + CS_ASSERT +}; + +struct xfer_cfg { + enum qspi_mode mode; +}; + +enum bus_xfer_direction { + MASTER_READ = 0, + MASTER_WRITE = 1, +}; + +struct { + struct cmd_desc descriptors[3]; + uint8_t buffers[3][CACHE_LINE_SIZE]; +} *dma = (void *)_dma_coherent; + +static void dma_transfer_chain(struct cmd_desc *chain) +{ + uint32_t mstr_int_status; + + write32(&sc7280_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7280_qspi->next_dma_desc_addr, (uint32_t)(uintptr_t) chain); + + while (1) { + mstr_int_status = read32(&sc7280_qspi->mstr_int_sts); + if (mstr_int_status & DMA_CHAIN_DONE) + break; + } +} + +static void flush_chain(void) +{ + struct cmd_desc *desc = &dma->descriptors[0]; + uint8_t *src; + uint8_t *dst; + + dma_transfer_chain(desc); + + while (desc) { + if (desc->direction == MASTER_READ) { + if (desc->bounce_length == 0) + dcache_invalidate_by_mva( + (void *)(uintptr_t) desc->data_address, + desc->length); + else { + src = (void *)(uintptr_t) desc->bounce_src; + dst = (void *)(uintptr_t) desc->bounce_dst; + memcpy(dst, src, desc->bounce_length); + } + } + desc = (void *)(uintptr_t) desc->next_descriptor; + } + curr_desc_idx = -1; +} + +static struct cmd_desc *allocate_descriptor(void) +{ + struct cmd_desc *current; + struct cmd_desc *next; + uint8_t index; + + current = (curr_desc_idx == -1) ? + NULL : &dma->descriptors[curr_desc_idx]; + + index = ++curr_desc_idx; + next = &dma->descriptors[index]; + + next->data_address = (uint32_t) (uintptr_t) dma->buffers[index]; + + next->next_descriptor = 0; + next->direction = MASTER_READ; + next->multi_io_mode = 0; + next->reserved1 = 0; + /* + * QSPI controller doesn't support transfer starts with read segment. + * So to support read transfers that are not preceded by write, set + * transfer fragment bit = 1 + */ + next->fragment = 1; + next->reserved2 = 0; + next->length = 0; + next->bounce_src = 0; + next->bounce_dst = 0; + next->bounce_length = 0; + + if (current) + current->next_descriptor = (uint32_t)(uintptr_t) next; + + return next; +} + +static void cs_change(enum cs_state state) +{ + gpio_set(GPIO(15), state == CS_DEASSERT); +} + +static void configure_gpios(void) +{ + gpio_output(GPIO(15), 1); + + gpio_configure(GPIO(12), GPIO12_FUNC_QSPI_DATA_0, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(13), GPIO13_FUNC_QSPI_DATA_1, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); + + gpio_configure(GPIO(14), GPIO14_FUNC_QSPI_CLK, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + uint8_t *ptr; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + ptr = (void *)(uintptr_t) desc->data_address; + + if (write) { + memcpy(ptr, data, data_bytes); + } else { + desc->bounce_src = (uint32_t)(uintptr_t) ptr; + desc->bounce_dst = (uint32_t)(uintptr_t) data; + desc->bounce_length = data_bytes; + } + + desc->length = data_bytes; +} + +static void queue_direct_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + struct cmd_desc *desc; + + desc = allocate_descriptor(); + desc->direction = write; + desc->multi_io_mode = data_mode; + desc->data_address = (uint32_t)(uintptr_t) data; + desc->length = data_bytes; + + if (write) + dcache_clean_by_mva(data, data_bytes); + else + dcache_invalidate_by_mva(data, data_bytes); +} + +static void queue_data(uint8_t *data, uint32_t data_bytes, + enum qspi_mode data_mode, bool write) +{ + uint8_t *aligned_ptr; + uint8_t *epilog_ptr; + uint32_t prolog_bytes, aligned_bytes, epilog_bytes; + + if (data_bytes == 0) + return; + + aligned_ptr = + (uint8_t *)ALIGN_UP((uintptr_t)data, CACHE_LINE_SIZE); + + prolog_bytes = MIN(data_bytes, aligned_ptr - data); + aligned_bytes = ALIGN_DOWN(data_bytes - prolog_bytes, CACHE_LINE_SIZE); + epilog_bytes = data_bytes - prolog_bytes - aligned_bytes; + + epilog_ptr = data + prolog_bytes + aligned_bytes; + + if (prolog_bytes) + queue_bounce_data(data, prolog_bytes, data_mode, write); + if (aligned_bytes) + queue_direct_data(aligned_ptr, aligned_bytes, data_mode, write); + if (epilog_bytes) + queue_bounce_data(epilog_ptr, epilog_bytes, data_mode, write); +} + +static void reg_init(void) +{ + uint32_t spi_mode; + uint32_t tx_data_oe_delay, tx_data_delay; + uint32_t mstr_config; + + spi_mode = 0; + + tx_data_oe_delay = 0; + tx_data_delay = 0; + + mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (spi_mode << SPI_MODE_SHIFT) | + (PIN_HOLDN) | + (FB_CLK_EN) | + (DMA_ENABLE) | + (FULL_CYCLE_MODE); + + write32(&sc7280_qspi->mstr_cfg, mstr_config); + write32(&sc7280_qspi->ahb_mstr_cfg, 0xA42); + write32(&sc7280_qspi->mstr_int_en, 0x0); + write32(&sc7280_qspi->mstr_int_sts, 0xFFFFFFFF); + write32(&sc7280_qspi->rd_fifo_cfg, 0x0); + write32(&sc7280_qspi->rd_fifo_rst, RESET_FIFO); +} + +void quadspi_init(uint32_t hz) +{ + assert(dcache_line_bytes() == CACHE_LINE_SIZE); + clock_configure_qspi(hz * 4); + configure_gpios(); + reg_init(); +} + +int sc7280_claim_bus(const struct spi_slave *slave) +{ + cs_change(CS_ASSERT); + return 0; +} + +void sc7280_release_bus(const struct spi_slave *slave) +{ + cs_change(CS_DEASSERT); +} + +static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, + void *din, size_t in_bytes) +{ + if ((out_bytes && !dout) || (in_bytes && !din) || + (in_bytes && out_bytes)) { + return -1; + } + + queue_data((uint8_t *) (out_bytes ? dout : din), + in_bytes | out_bytes, mode, !!out_bytes); + + flush_chain(); + + return 0; +} + +int sc7280_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_1BIT, dout, out_bytes, din, in_bytes); +} + +int sc7280_xfer_dual(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) +{ + return xfer(SDR_2BIT, dout, out_bytes, din, in_bytes); +} diff --git a/src/soc/qualcomm/sc7280/spi.c b/src/soc/qualcomm/sc7280/spi.c index 50aa395..61ccd86 100644 --- a/src/soc/qualcomm/sc7280/spi.c +++ b/src/soc/qualcomm/sc7280/spi.c @@ -2,12 +2,19 @@ #include <spi-generic.h> #include <spi_flash.h> +#include <soc/qspi.h> -static const struct spi_ctrlr spi_ctrlr; +static const struct spi_ctrlr qspi_ctrlr = { + .claim_bus = sc7280_claim_bus, + .release_bus = sc7280_release_bus, + .xfer = sc7280_xfer, + .xfer_dual = sc7280_xfer_dual, + .max_xfer_size = QSPI_MAX_PACKET_COUNT, +}; const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { - .ctrlr = &spi_ctrlr, + .ctrlr = &qspi_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/47075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d4159939a57648c54dcb06aea3645f1dfe10903 Gerrit-Change-Number: 47075 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak, Sridhar Siricilla. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 08:42:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Replace EDK2 code
by Arthur Heymans (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Jeff Daly, Patrick Rudolph, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62985 ) Change subject: soc/intel/denverton_ns: Replace EDK2 code ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Gerrit-Change-Number: 62985 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 08:41:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Replace EDK2 code
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio. Hello Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62985 to look at the new patch set (#3). Change subject: soc/intel/denverton_ns: Replace EDK2 code ...................................................................... soc/intel/denverton_ns: Replace EDK2 code Replace LShiftU64 and RShiftU64 as the defined macro conflicts with UDK2017 headers. Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/denverton_ns/gpio_dnv.c M src/soc/intel/denverton_ns/include/soc/gpio_dnv.h 2 files changed, 13 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/62985/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f205f663be9c9c31cf384ca89370afa48ca1e15 Gerrit-Change-Number: 62985 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: herobrine: SoC makefile blob support
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47074 ) Change subject: herobrine: SoC makefile blob support ...................................................................... herobrine: SoC makefile blob support Following blobs will includes with SoC makefile: * QCSEC * QUPV3FW Change-Id: Ic76af29440a6ef3a458381d63a819f5a1843e111 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/Makefile.inc 1 file changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/47074/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index 6d07629..d6f8d29 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -44,4 +44,28 @@ @util/qualcomm/qgpt.py $(objcbfs)/merged_bb_qcsec.mbn \ $(objcbfs)/bootblock.bin +################################################################################ +UART_FW_FILE := $(SC7280_BLOB)/qup_fw/uart_fw.bin +UART_FW_CBFS := $(CONFIG_CBFS_PREFIX)/uart_fw +$(UART_FW_CBFS)-file := $(UART_FW_FILE) +$(UART_FW_CBFS)-type := raw +$(UART_FW_CBFS)-compression := none +cbfs-files-y += $(UART_FW_CBFS) + +################################################################################ +SPI_FW_FILE := $(SC7280_BLOB)/qup_fw/spi_fw.bin +SPI_FW_CBFS := $(CONFIG_CBFS_PREFIX)/spi_fw +$(SPI_FW_CBFS)-file := $(SPI_FW_FILE) +$(SPI_FW_CBFS)-type := raw +$(SPI_FW_CBFS)-compression := none +cbfs-files-y += $(SPI_FW_CBFS) + +################################################################################ +I2C_FW_FILE := $(SC7280_BLOB)/qup_fw/i2c_fw.bin +I2C_FW_CBFS := $(CONFIG_CBFS_PREFIX)/i2c_fw +$(I2C_FW_CBFS)-file := $(I2C_FW_FILE) +$(I2C_FW_CBFS)-type := raw +$(I2C_FW_CBFS)-compression := none +cbfs-files-y += $(I2C_FW_CBFS) + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/47074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic76af29440a6ef3a458381d63a819f5a1843e111 Gerrit-Change-Number: 47074 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: SC7280: Add GPIO driver in coreboot
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47077 ) Change subject: SC7280: Add GPIO driver in coreboot ...................................................................... SC7280: Add GPIO driver in coreboot Add support for gpio driver for SC7280 Change-Id: Ibefa2fc04db09f1837f65f5a6d4b8534df040785 --- M src/soc/qualcomm/sc7280/Makefile.inc A src/soc/qualcomm/sc7280/gpio.c M src/soc/qualcomm/sc7280/include/soc/addressmap.h M src/soc/qualcomm/sc7280/include/soc/gpio.h 4 files changed, 378 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/47077/1 diff --git a/src/soc/qualcomm/sc7280/Makefile.inc b/src/soc/qualcomm/sc7280/Makefile.inc index f94a425..a6112b3 100644 --- a/src/soc/qualcomm/sc7280/Makefile.inc +++ b/src/soc/qualcomm/sc7280/Makefile.inc @@ -8,12 +8,14 @@ bootblock-y += spi.c bootblock-$(CONFIG_SC7280_QSPI) += qspi.c bootblock-y += clock.c +bootblock-y += gpio.c ################################################################################ verstage-y += timer.c verstage-y += spi.c verstage-$(CONFIG_SC7280_QSPI) += qspi.c verstage-y += clock.c +verstage-y += gpio.c ################################################################################ romstage-y += cbmem.c @@ -25,6 +27,7 @@ romstage-y += spi.c romstage-$(CONFIG_SC7280_QSPI) += qspi.c romstage-y += clock.c +romstage-y += gpio.c ################################################################################ ramstage-y += soc.c @@ -33,6 +36,7 @@ ramstage-y += spi.c ramstage-$(CONFIG_SC7280_QSPI) += qspi.c ramstage-y += clock.c +ramstage-y += gpio.c ################################################################################ diff --git a/src/soc/qualcomm/sc7280/gpio.c b/src/soc/qualcomm/sc7280/gpio.c new file mode 100644 index 0000000..67204e8 --- /dev/null +++ b/src/soc/qualcomm/sc7280/gpio.c @@ -0,0 +1,89 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <device/mmio.h> +#include <types.h> + +#include <gpio.h> + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable) +{ + uint32_t reg_val; + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + /* gpio pull only PULLNONE, PULLUP, KEEPER, PULLDOWN status */ + assert(pull <= GPIO_PULL_UP); + + reg_val = ((enable & GPIO_CFG_OE_BMSK) << GPIO_CFG_OE_SHFT) | + ((drive_str & GPIO_CFG_DRV_BMSK) << GPIO_CFG_DRV_SHFT) | + ((func & GPIO_CFG_FUNC_BMSK) << GPIO_CFG_FUNC_SHFT) | + ((pull & GPIO_CFG_PULL_BMSK) << GPIO_CFG_PULL_SHFT); + + write32(&regs->cfg, reg_val); +} + +void gpio_set(gpio_t gpio, int value) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + write32(&regs->in_out, (!!value) << GPIO_IO_OUT_SHFT); +} + +int gpio_get(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + return ((read32(&regs->in_out) >> GPIO_IO_IN_SHFT) & + GPIO_IO_IN_BMSK); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_DOWN, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input_pullup(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_PULL_UP, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_input(gpio_t gpio) +{ + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_DISABLE); +} + +void gpio_output(gpio_t gpio, int value) +{ + gpio_set(gpio, value); + gpio_configure(gpio, GPIO_FUNC_GPIO, + GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); +} + +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + gpio_configure(gpio, GPIO_FUNC_GPIO, + pull, GPIO_2MA, GPIO_OUTPUT_DISABLE); + + clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK << + GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT); + clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE + << GPIO_INTR_RAW_STATUS_EN_SHIFT); +} + +int gpio_irq_status(gpio_t gpio) +{ + struct tlmm_gpio *regs = (void *)(uintptr_t)gpio.addr; + + if (!(read32(&regs->intr_status) & GPIO_INTR_STATUS_MASK)) + return 0; + + write32(&regs->intr_status, GPIO_INTR_STATUS_DISABLE); + return 1; +} diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index ae31b1c..d2e50f2 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -8,5 +8,6 @@ #define AOSS_CC_BASE 0x0C2A0000 #define GCC_BASE 0x00100000 #define QSPI_BASE 0x088DC000 +#define TLMM_TILE_BASE 0x0F100000 #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/gpio.h b/src/soc/qualcomm/sc7280/include/soc/gpio.h index 82a0c39..744ba49 100644 --- a/src/soc/qualcomm/sc7280/include/soc/gpio.h +++ b/src/soc/qualcomm/sc7280/include/soc/gpio.h @@ -4,9 +4,293 @@ #define _SOC_QUALCOMM_SC7280_GPIO_H_ #include <types.h> +#include <soc/addressmap.h> typedef struct { u32 addr; } gpio_t; +#define TLMM_TILE_SIZE 0x00300000 +#define TLMM_GPIO_OFF_DELTA 0x1000 + +#define TLMM_GPIO_IN_OUT_OFF 0x4 +#define TLMM_GPIO_ID_STATUS_OFF 0x10 + +#define GPIO_FUNC_GPIO 0 + +/* GPIO INTR CFG MASK */ +#define GPIO_INTR_DECT_CTL_MASK 0x3 +#define GPIO_INTR_RAW_STATUS_EN_MASK 0x1 + +/* GPIO INTR CFG SHIFT */ +#define GPIO_INTR_DECT_CTL_SHIFT 2 +#define GPIO_INTR_RAW_STATUS_EN_SHIFT 4 + +/* GPIO INTR STATUS MASK */ +#define GPIO_INTR_STATUS_MASK 0x1 + +/* GPIO INTR RAW STATUS */ +#define GPIO_INTR_RAW_STATUS_ENABLE 1 +#define GPIO_INTR_RAW_STATUS_DISABLE 0 + +/* GPIO INTR STATUS */ +#define GPIO_INTR_STATUS_ENABLE 1 +#define GPIO_INTR_STATUS_DISABLE 0 + +/* GPIO TLMM: Direction */ +#define GPIO_INPUT 0 +#define GPIO_OUTPUT 1 + +/* GPIO TLMM: Pullup/Pulldown */ +#define GPIO_NO_PULL 0 +#define GPIO_PULL_DOWN 1 +#define GPIO_KEEPER 2 +#define GPIO_PULL_UP 3 + +/* GPIO TLMM: Drive Strength */ +#define GPIO_2MA 0 +#define GPIO_4MA 1 +#define GPIO_6MA 2 +#define GPIO_8MA 3 +#define GPIO_10MA 4 +#define GPIO_12MA 5 +#define GPIO_14MA 6 +#define GPIO_16MA 7 + +/* GPIO TLMM: Status */ +#define GPIO_OUTPUT_DISABLE 0 +#define GPIO_OUTPUT_ENABLE 1 + +/* GPIO TLMM: Mask */ +#define GPIO_CFG_PULL_BMSK 0x3 +#define GPIO_CFG_FUNC_BMSK 0xF +#define GPIO_CFG_DRV_BMSK 0x7 +#define GPIO_CFG_OE_BMSK 0x1 + +/* GPIO TLMM: Shift */ +#define GPIO_CFG_PULL_SHFT 0 +#define GPIO_CFG_FUNC_SHFT 2 +#define GPIO_CFG_DRV_SHFT 6 +#define GPIO_CFG_OE_SHFT 9 + +/* GPIO IO: Mask */ +#define GPIO_IO_IN_BMSK 0x1 +#define GPIO_IO_OUT_BMSK 0x1 + +/* GPIO IO: Shift */ +#define GPIO_IO_IN_SHFT 0 +#define GPIO_IO_OUT_SHFT 1 + +/* GPIO ID STATUS: Mask */ +#define GPIO_ID_STATUS_BMSK 0x1 + +/* GPIO MAX Valid # */ +#define GPIO_NUM_MAX 174 + +#define GPIO(num) ((gpio_t){.addr = GPIO##num##_ADDR}) + +#define PIN(index, func1, func2, func3, func4) \ +GPIO##index##_ADDR = TLMM_TILE_BASE + index * TLMM_GPIO_OFF_DELTA, \ +GPIO##index##_FUNC_##func1 = 1, \ +GPIO##index##_FUNC_##func2 = 2, \ +GPIO##index##_FUNC_##func3 = 3, \ +GPIO##index##_FUNC_##func4 = 4 + +enum { + PIN(0, QUP0_L0, RES_2, RES_3, RES_4), + PIN(1, QUP0_L1, RES_2, RES_3, RES_4), + PIN(2, QUP0_L2, QUP0_L4, RES_3, RES_4), + PIN(3, QUP0_L3, QUP0_L5, RES_3, RES_4), + PIN(4, QUP0_L0, RES_2, RES_3, RES_4), + PIN(5, QUP0_L1, RES_2, RES_3, RES_4), + PIN(6, QUP0_L2, QUP0_L6, RES_3, RES_4), + PIN(7, USB_AUDIO_INT_N__SBU_SW_OE, QUP0_L3, RES_3, RES_4), + PIN(8, QUP0_L0, RES_2, RES_3, RES_4), + PIN(9, QUP0_L1, RES_2, RES_3, RES_4), + PIN(10, GNSS_ELNA_EN0, QUP0_L2, RES_3, RES_4), + PIN(11, GNSS_ELNA_EN1, QUP0_L3, RES_3, RES_4), + PIN(12, QUP0_L0, QSPI_DATA_0, RES_3, RES_4), + PIN(13, QUP0_L1, QSPI_DATA_1, RES_3, RES_4), + PIN(14, QUP0_L2, QSPI_CLK, RES_3, RES_4), + PIN(15, QUP0_L3, QSPI_CS_N_0, RES_3, RES_4), + PIN(16, QUP0_L0, QSPI_DATA_2, RES_3, RES_4), + PIN(17, QUP0_L1, QSPI_DATA_3, RES_3, RES_4), + PIN(18, QUP0_L2, RES_2, RES_3, RES_4), + PIN(19, QUP0_L3, QSPI_CS_N_1, RES_3, RES_4), + PIN(20, QUP0_L0, CCI_TIMER_0, RES_3, RES_4), + PIN(21, QUP0_L1, CCI_TIMER_1, RES_3, RES_4), + PIN(22, QUP0_L2, RES_2, RES_3, RES_4), + PIN(23, QUP0_L3, RES_2, RES_3, RES_4), + PIN(24, QUP0_L0, RES_2, RES_3, RES_4), + PIN(25, QUP0_L1, RES_2, RES_3, RES_4), + PIN(26, QUP0_L2, RES_2, RES_3, RES_4), + PIN(27, QUP0_L3, RES_2, RES_3, RES_4), + PIN(28, QUP0_L0, RES_2, RES_3, RES_4), + PIN(29, QUP0_L1, RES_2, RES_3, RES_4), + PIN(30, QUP0_L2, RES_2, RES_3, RES_4), + PIN(31, QUP0_L3, RES_2, RES_3, RES_4), + PIN(32, QUP1_L0, RES_2, RES_3, RES_4), + PIN(33, QUP1_L1, RES_2, RES_3, RES_4), + PIN(34, QUP1_L2, RES_2, RES_3, RES_4), + PIN(35, QUP1_L3, RES_2, RES_3, RES_4), + PIN(36, QUP1_L0, RES_2, RES_3, RES_4), + PIN(37, QUP1_L1, RES_2, RES_3, RES_4), + PIN(38, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(39, QUP1_L3, RES_2, RES_3, RES_4), + PIN(40, QUP1_L0, RES_2, RES_3, RES_4), + PIN(41, QUP1_L1, RES_2, RES_3, RES_4), + PIN(42, QUP1_L2, RES_2, RES_3, RES_4), + PIN(43, QUP1_L3, RES_2, RES_3, RES_4), + PIN(44, QUP1_L0, RES_2, RES_3, RES_4), + PIN(45, QUP1_L1, RES_2, RES_3, RES_4), + PIN(46, QUP1_L2, RES_2, RES_3, RES_4), + PIN(47, QUP1_L3, DP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(48, QUP1_L0, RES_2, RES_3, RES_4), + PIN(49, QUP1_L1, RES_2, RES_3, RES_4), + PIN(50, QUP1_L2, QUP1_L6, RES_3, RES_4), + PIN(51, QUP1_L3, RES_2, RES_3, RES_4), + PIN(52, QUP1_L0, RES_2, RES_3, RES_4), + PIN(53, QUP1_L1, RES_2, RES_3, RES_4), + PIN(54, QUP1_L2, QUP1_L5, RES_3, RES_4), + PIN(55, QUP1_L3, QUP1_L4, RES_3, RES_4), + PIN(56, QUP1_L0, RES_2, RES_3, RES_4), + PIN(57, QUP1_L1, RES_2, RES_3, RES_4), + PIN(58, QUP1_L2, RES_2, RES_3, RES_4), + PIN(59, QUP1_L3, RES_2, RES_3, RES_4), + PIN(60, QUP1_L0, EDP_HOT_PLUG_DETECT, RES_3, RES_4), + PIN(61, QUP1_L1, SD_WRITE_PROTECT, RES_3, RES_4), + PIN(62, QUP1_L2, QUP1_L4, RES_3, RES_4), + PIN(63, QUP1_L3, QUP1_L5, RES_3, RES_4), + PIN(64, CAM_MCLK0, RES_2, RES_3, RES_4), + PIN(65, CAM_MCLK1, RES_2, RES_3, RES_4), + PIN(66, CAM_MCLK2, RES_2, RES_3, RES_4), + PIN(67, CAM_MCLK3, RES_2, RES_3, RES_4), + PIN(68, CAM_MCLK4, RES_2, RES_3, RES_4), + PIN(69, CCI_I2C_SDA0, RES_2, RES_3, RES_4), + PIN(70, CCI_I2C_SCL0, RES_2, RES_3, RES_4), + PIN(71, CCI_I2C_SDA1, RES_2, RES_3, RES_4), + PIN(72, CCI_I2C_SCL1, RES_2, RES_3, RES_4), + PIN(73, CCI_I2C_SDA2, RES_2, RES_3, RES_4), + PIN(74, CCI_I2C_SCL2, RES_2, RES_3, RES_4), + PIN(75, CCI_I2C_SDA3, RES_2, RES_3, RES_4), + PIN(76, CCI_I2C_SCL3, GCC_GP1_CLK_MIRB, RES_3, RES_4), + PIN(77, CCI_TIMER2, GCC_GP2_CLK_MIRB, RES_3, RES_4), + PIN(78, CCI_TIMER3, CCI_ASYNC_IN1, GCC_GP3_CLK_MIRB, RES_4), + PIN(79, CCI_TIMER4, CCI_ASYNC_IN2, RES_3, RES_4), + PIN(80, RES_1, RES_2, RES_3, RES_4), + PIN(81, RES_1, RES_2, RES_3, RES_4), + PIN(82, RES_1, RES_2, RES_3, RES_4), + PIN(83, RES_1, RES_2, RES_3, RES_4), + PIN(84, USB2PHY_AC_EN0, RES_2, RES_3, RES_4), + PIN(85, USB2PHY_AC_EN1, RES_2, RES_3, RES_4), + PIN(86, RES_1, RES_2, RES_3, RES_4), + PIN(87, RES_1, RES_2, RES_3, RES_4), + PIN(88, RES_1, RES_2, RES_3, RES_4), + PIN(89, RES_1, RES_2, RES_3, RES_4), + PIN(90, RES_1, RES_2, RES_3, RES_4), + PIN(91, RES_1, RES_2, RES_3, RES_4), + PIN(92, RES_1, RES_2, RES_3, RES_4), + PIN(93, CAM_MCLK5, CCI_ASYNC_IN0, RES_3, RES_4), + PIN(94, LPASS_SLIMBUS_CLK, RES_2, RES_3, RES_4), + PIN(95, LPASS_SLIMBUS_DATA0, RES_2, RES_3, RES_4), + PIN(96, PRI_MI2S_MCLK, RES_2, RES_3, RES_4), + PIN(97, MI2S0_SCK, RES_2, RES_3, RES_4), + PIN(98, MI2S0_DATA0, RES_2, RES_3, RES_4), + PIN(99, MI2S0_DATA1, RES_2, RES_3, RES_4), + PIN(100, MI2S0_WS, RES_2, RES_3, RES_4), + PIN(101, MI2S2_SCK, RES_2, RES_3, RES_4), + PIN(102, MI2S2_DATA0, RES_2, RES_3, RES_4), + PIN(103, MI2S2_WS, RES_2, RES_3, RES_4), + PIN(104, MI2S2_DATA1, RES_2, RES_3, RES_4), + PIN(105, SEC_MI2S_MCLK, MI2S1_DATA1, RES_3, GCC_GP1_CLK_MIRA), + PIN(106, MI2S1_SCK, GCC_GP2_CLK_MIRA, RES_3, RES_4), + PIN(107, MI2S1_DATA0, GCC_GP3_CLK_MIRA, RES_3, RES_4), + PIN(108, MI2S1_WS, RES_2, RES_3, RES_4), + PIN(109, RES_1, RES_2, RES_3, RES_4), + PIN(110, RES_1, RES_2, RES_3, RES_4), + PIN(111, RES_1, RES_2, RES_3, RES_4), + PIN(112, RES_1, RES_2, RES_3, RES_4), + PIN(113, RES_1, RES_2, RES_3, RES_4), + PIN(114, RES_1, RES_2, RES_3, RES_4), + PIN(115, RES_1, RES_2, RES_3, RES_4), + PIN(116, RES_1, RES_2, RES_3, RES_4), + PIN(117, RES_1, RES_2, RES_3, RES_4), + PIN(118, RES_1, RES_2, RES_3, RES_4), + PIN(119, RES_1, RES_2, RES_3, RES_4), + PIN(120, RES_1, RES_2, RES_3, RES_4), + PIN(121, RES_1, RES_2, RES_3, RES_4), + PIN(122, RES_1, RES_2, RES_3, RES_4), + PIN(123, RES_1, RES_2, RES_3, RES_4), + PIN(124, RES_1, RES_2, RES_3, RES_4), + PIN(125, RES_1, RES_2, RES_3, RES_4), + PIN(126, RES_1, RES_2, RES_3, RES_4), + PIN(127, RES_1, RES_2, RES_3, RES_4), + PIN(128, RES_1, RES_2, RES_3, RES_4), + PIN(129, RES_1, RES_2, RES_3, RES_4), + PIN(130, RES_1, RES_2, RES_3, RES_4), + PIN(131, RES_1, RES_2, RES_3, RES_4), + PIN(132, RES_1, RES_2, RES_3, RES_4), + PIN(133, RES_1, RES_2, RES_3, RES_4), + PIN(134, RES_1, RES_2, RES_3, RES_4), + PIN(135, RES_1, RES_2, RES_3, RES_4), + PIN(136, RES_1, RES_2, RES_3, RES_4), + PIN(137, RES_1, RES_2, RES_3, RES_4), + PIN(138, RES_1, RES_2, RES_3, RES_4), + PIN(139, RES_1, RES_2, RES_3, RES_4), + PIN(140, USB_PHY_PS, RES_2, RES_3, RES_4), + PIN(141, RES_1, RES_2, RES_3, RES_4), + PIN(142, RES_1, RES_2, RES_3, RES_4), + PIN(143, RES_1, RES_2, RES_3, RES_4), + PIN(144, RES_1, RES_2, RES_3, RES_4), + PIN(145, RES_1, RES_2, RES_3, RES_4), + PIN(146, RES_1, RES_2, RES_3, RES_4), + PIN(147, RES_1, RES_2, RES_3, RES_4), + PIN(148, RES_1, RES_2, RES_3, RES_4), + PIN(149, RES_1, RES_2, RES_3, RES_4), + PIN(150, RES_1, RES_2, RES_3, RES_4), + PIN(151, RES_1, RES_2, RES_3, RES_4), + PIN(152, RES_1, RES_2, RES_3, RES_4), + PIN(153, RES_1, RES_2, RES_3, RES_4), + PIN(154, RES_1, RES_2, RES_3, RES_4), + PIN(155, RES_1, RES_2, RES_3, RES_4), + PIN(156, RES_1, RES_2, RES_3, RES_4), + PIN(157, RES_1, RES_2, RES_3, RES_4), + PIN(158, RES_1, RES_2, RES_3, RES_4), + PIN(159, RES_1, RES_2, RES_3, RES_4), + PIN(160, RES_1, RES_2, RES_3, RES_4), + PIN(161, RES_1, RES_2, RES_3, RES_4), + PIN(162, RES_1, RES_2, RES_3, RES_4), + PIN(163, RES_1, RES_2, RES_3, RES_4), + PIN(164, RES_1, RES_2, RES_3, RES_4), + PIN(165, RES_1, RES_2, RES_3, RES_4), + PIN(166, RES_1, RES_2, RES_3, RES_4), + PIN(167, RES_1, RES_2, RES_3, RES_4), + PIN(168, RES_1, RES_2, RES_3, RES_4), + PIN(169, RES_1, RES_2, RES_3, RES_4), + PIN(170, RES_1, RES_2, RES_3, RES_4), + PIN(171, RES_1, RES_2, RES_3, RES_4), + PIN(172, RES_1, RES_2, RES_3, RES_4), + PIN(173, RES_1, RES_2, RES_3, RES_4), + PIN(174, RES_1, RES_2, RES_3, RES_4), +}; + +enum gpio_irq_type { + IRQ_TYPE_LEVEL = 0, + IRQ_TYPE_RISING_EDGE = 1, + IRQ_TYPE_FALLING_EDGE = 2, + IRQ_TYPE_DUAL_EDGE = 3, +}; + +struct tlmm_gpio { + uint32_t cfg; + uint32_t in_out; + uint32_t intr_cfg; + uint32_t intr_status; +}; + +void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, + uint32_t drive_str, uint32_t enable); +void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull); +int gpio_irq_status(gpio_t gpio); + #endif /* _SOC_QUALCOMM_SC7280_GPIO_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/47077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibefa2fc04db09f1837f65f5a6d4b8534df040785 Gerrit-Change-Number: 47077 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

6 58

Change in coreboot[master]: sc7280: Add PCIe Root Complex driver in coreboot
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52375 ) Change subject: sc7280: Add PCIe Root Complex driver in coreboot ...................................................................... Abandoned abandon these changes as already review is going with separate CL: https://review.coreboot.org/c/coreboot/+/53902 -- To view, visit https://review.coreboot.org/c/coreboot/+/52375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I850fc43c840629667ac1c6de897306adb5a907e5 Gerrit-Change-Number: 52375 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: HACK payloads: Add libpci for arm arch HACK
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/52376 ) Change subject: HACK payloads: Add libpci for arm arch HACK ...................................................................... Abandoned abandon these changes as already review is going with separate CL: https://review.coreboot.org/c/coreboot/+/53902 -- To view, visit https://review.coreboot.org/c/coreboot/+/52376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9850125d27da9d7bec3fc3af9995c6db240b4b3d Gerrit-Change-Number: 52376 Gerrit-PatchSet: 5 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: HACK sc7280: include sc7280 qc_blobs HACK
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/51338 ) Change subject: HACK sc7280: include sc7280 qc_blobs HACK ...................................................................... Abandoned abandon these changes as already merged: https://review.coreboot.org/c/coreboot/+/52536 -- To view, visit https://review.coreboot.org/c/coreboot/+/51338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa54f386256ec90f5fd5b4b732e5ca0a7c869551 Gerrit-Change-Number: 51338 Gerrit-PatchSet: 26 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

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