coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: Standalone coreboot fix and qclib memlayout changes
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Hello Sudheer Amrabadi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/49013 to review the following change. Change subject: Standalone coreboot fix and qclib memlayout changes ...................................................................... Standalone coreboot fix and qclib memlayout changes Change-Id: Ie477d7c17060c2c6b657cc55ab44a79312caec4a --- M src/soc/qualcomm/sc7280/memlayout.ld M src/soc/qualcomm/sc7280/qclib.c M src/soc/qualcomm/sc7280/qupv3_config.c 3 files changed, 13 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/49013/1 diff --git a/src/soc/qualcomm/sc7280/memlayout.ld b/src/soc/qualcomm/sc7280/memlayout.ld index fed3a72..2d6e207 100644 --- a/src/soc/qualcomm/sc7280/memlayout.ld +++ b/src/soc/qualcomm/sc7280/memlayout.ld @@ -40,11 +40,12 @@ REGION(qclib_serial_log, 0x14857000, 4K, 4K) REGION(ddr_information, 0x1485B000, 1K, 1K) FMAP_CACHE(0x1485B400, 2K) - REGION(dcb, 0x1485F000, 16K, 4K) - REGION(pmic, 0x14863000, 44K, 4K) - REGION(limits_cfg, 0x1486E000, 4K, 4K) - REGION(qclib, 0x1486F000, 596K, 4K) - BSRAM_END(0x14904000) + CBFS_MCACHE(0x1485BC00,8K) + REGION(dcb, 0x14875000, 32K, 4K) + REGION(pmic, 0x1487D000, 92K, 4K) + REGION(limits_cfg, 0x14894000, 4K, 4K) + REGION(qclib, 0x14895000, 748K, 4K) + BSRAM_END(0x14950000) DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ diff --git a/src/soc/qualcomm/sc7280/qclib.c b/src/soc/qualcomm/sc7280/qclib.c old mode 100644 new mode 100755 index 6affc63..d1fca2f --- a/src/soc/qualcomm/sc7280/qclib.c +++ b/src/soc/qualcomm/sc7280/qclib.c @@ -12,15 +12,15 @@ ssize_t ssize; /* Attempt to load PMICCFG Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/pmiccfg", - _pmic, REGION_SIZE(pmic), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/pmiccfg", + _pmic, REGION_SIZE(pmic)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_PMIC_SETTINGS, _pmic, size, 0); /* Attempt to load DCB Blob */ - size = cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/dcb", - _dcb, REGION_SIZE(dcb), CBFS_TYPE_RAW); + size = cbfs_load(CONFIG_CBFS_PREFIX "/dcb", + _dcb, REGION_SIZE(dcb)); if (!size) return -1; qclib_add_if_table_entry(QCLIB_TE_DCB_SETTINGS, _dcb, size, 0); diff --git a/src/soc/qualcomm/sc7280/qupv3_config.c b/src/soc/qualcomm/sc7280/qupv3_config.c old mode 100644 new mode 100755 index 3dbe3e6..66b1534 --- a/src/soc/qualcomm/sc7280/qupv3_config.c +++ b/src/soc/qualcomm/sc7280/qupv3_config.c @@ -26,10 +26,10 @@ die("*ERROR* * INVALID PROTOCOL ***\n"); if (!fw_list[protocol]) { - fw_list[protocol] = cbfs_boot_map_with_leak(filename[protocol], - CBFS_TYPE_RAW, NULL); + fw_list[protocol] = cbfs_map(filename[protocol], + NULL); if (!fw_list[protocol]) - die("*ERROR* * cbfs_boot_map_with_leak failed ***\n"); + die("*ERROR* * cbfs_map() failed ***\n"); } hdr = fw_list[protocol]; -- To view, visit https://review.coreboot.org/c/coreboot/+/49013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie477d7c17060c2c6b657cc55ab44a79312caec4a Gerrit-Change-Number: 49013 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Sudheer Amrabadi <samrab(a)codeaurora.org> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: sc7280: HACK PATCH: UART source clock frequency change
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47528 ) Change subject: sc7280: HACK PATCH: UART source clock frequency change ...................................................................... sc7280: HACK PATCH: UART source clock frequency change On SoC, console UART works fine with 19.2MHz On Rumi, facing issues with 19.2MHz and changed it to 7372800Hz Change-Id: I7e91d704f51290d4e368972d53fde59161936c3f Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/qupv3_uart.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/47528/1 diff --git a/src/soc/qualcomm/sc7280/qupv3_uart.c b/src/soc/qualcomm/sc7280/qupv3_uart.c index 5679a25..c9ae1ab 100644 --- a/src/soc/qualcomm/sc7280/qupv3_uart.c +++ b/src/soc/qualcomm/sc7280/qupv3_uart.c @@ -71,7 +71,7 @@ /* sc7280 requires 16 clock pulses to sample 1 bit of data */ uart_freq = baud_rate * 16; - div = DIV_ROUND_CLOSEST(SRC_XO_HZ, uart_freq); + div = DIV_ROUND_CLOSEST(7372800, uart_freq); write32(&regs->geni_ser_m_clk_cfg, (div << 4) | 1); write32(&regs->geni_ser_s_clk_cfg, (div << 4) | 1); -- To view, visit https://review.coreboot.org/c/coreboot/+/47528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e91d704f51290d4e368972d53fde59161936c3f Gerrit-Change-Number: 47528 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sc7280: clk: shrm: API for SHRM out of Reset
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/49393 ) Change subject: sc7280: clk: shrm: API for SHRM out of Reset ...................................................................... Abandoned abandon these changes are merged with this CL: https://review.coreboot.org/c/coreboot/+/50580 -- To view, visit https://review.coreboot.org/c/coreboot/+/49393 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97cd5582fe5c1d0f85eb88e7aca0be55ddccc317 Gerrit-Change-Number: 49393 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: HACK sc7280: fix assertion error while booting in clock initialization
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47146 ) Change subject: HACK sc7280: fix assertion error while booting in clock initialization ...................................................................... HACK sc7280: fix assertion error while booting in clock initialization Julius patch for reference: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/… Change-Id: If10647ff3639c4b98180569352a18625749f2756 --- M src/soc/qualcomm/sc7280/bootblock.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47146/1 diff --git a/src/soc/qualcomm/sc7280/bootblock.c b/src/soc/qualcomm/sc7280/bootblock.c index 49c9e18..09e95f2 100644 --- a/src/soc/qualcomm/sc7280/bootblock.c +++ b/src/soc/qualcomm/sc7280/bootblock.c @@ -8,6 +8,6 @@ void bootblock_soc_init(void) { sc7280_mmu_init(); - quadspi_init(37500 * KHz); + quadspi_init(25 * MHz); clock_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If10647ff3639c4b98180569352a18625749f2756 Gerrit-Change-Number: 47146 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib exec...
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47080 ) Change subject: sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib execution ...................................................................... sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib execution Change-Id: I213f6063ba8a06740488f44dabf377659bb70579 --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/mmu.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47080/1 diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 8844f18..9927677 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -6,5 +6,5 @@ void platform_romstage_main(void) { /* QCLib: DDR init & train */ - qclib_load_and_run(); + //qclib_load_and_run(); } diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c index 9905c29..f6e85a6 100644 --- a/src/soc/qualcomm/sc7280/mmu.c +++ b/src/soc/qualcomm/sc7280/mmu.c @@ -16,6 +16,8 @@ mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM); mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent), UNCACHED_RAM); + mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM); + mmu_config_range((void *)(2UL * GiB), (2UL * GiB) , CACHED_RAM); mmu_enable(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/47080 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I213f6063ba8a06740488f44dabf377659bb70579 Gerrit-Change-Number: 47080 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

3 16

Change in coreboot[master]: sc7280: HACK PATCH: To support SPI-NOR driver for Rumi
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47079 ) Change subject: sc7280: HACK PATCH: To support SPI-NOR driver for Rumi ...................................................................... sc7280: HACK PATCH: To support SPI-NOR driver for Rumi - In Rumi, GPIO emulation is not present and CS assert/deassert is done through controller - In soc, CS assert/deassert is done using GPIO - Disable SBL_EN bit in QSPI master config register Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/qspi.c 1 file changed, 10 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/47079/1 diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index 3c627a5..fba8f89 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -123,15 +123,17 @@ * So to support read transfers that are not preceded by write, set * transfer fragment bit = 1 */ - next->fragment = 1; + next->fragment = 0; next->reserved2 = 0; next->length = 0; next->bounce_src = 0; next->bounce_dst = 0; next->bounce_length = 0; - if (current) + if (current) { current->next_descriptor = (uint32_t)(uintptr_t) next; + current->fragment = 1; + } return next; } @@ -169,6 +171,7 @@ ptr = (void *)(uintptr_t) desc->data_address; if (write) { + desc->fragment = 1; memcpy(ptr, data, data_bytes); } else { desc->bounce_src = (uint32_t)(uintptr_t) ptr; @@ -190,10 +193,12 @@ desc->data_address = (uint32_t)(uintptr_t) data; desc->length = data_bytes; - if (write) + if (write) { + desc->fragment = 1; dcache_clean_by_mva(data, data_bytes); - else + } else { dcache_invalidate_by_mva(data, data_bytes); + } } static void queue_data(uint8_t *data, uint32_t data_bytes, @@ -235,7 +240,7 @@ tx_data_delay = 0; mstr_config = (tx_data_oe_delay << TX_DATA_OE_DELAY_SHIFT) | - (tx_data_delay << TX_DATA_DELAY_SHIFT) | (SBL_EN) | + (tx_data_delay << TX_DATA_DELAY_SHIFT) | (spi_mode << SPI_MODE_SHIFT) | (PIN_HOLDN) | (FB_CLK_EN) | -- To view, visit https://review.coreboot.org/c/coreboot/+/47079 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a53c1094b90ac7896e835864848467c52d2a03e Gerrit-Change-Number: 47079 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: Kconfig: Select UDK2017
by Patrick Rudolph (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio. Hello build bot (Jenkins), Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62984 to look at the new patch set (#5). Change subject: Kconfig: Select UDK2017 ...................................................................... Kconfig: Select UDK2017 On platforms using UDK2015 select UDK2017 instead. This allows to drop UDK2015 headers. Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/intel/galileo/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/skylake/Kconfig 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/62984/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6032c6520ec889cd63655db982d9bfa476dc24d Gerrit-Change-Number: 62984 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: HACK PATCH: sc7280: Comment out gpio and clock dependency
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47078 ) Change subject: HACK PATCH: sc7280: Comment out gpio and clock dependency ...................................................................... HACK PATCH: sc7280: Comment out gpio and clock dependency As clock and gpio supports are not yet present in kodiak build, commenting out those inorder to compile QSPI driver. Change-Id: I148a7bd7910a6d23cbec354fe88b35644a8716bf Signed-off-by: Roja Rani Yarubandi <rojay(a)codeaurora.org> --- M src/soc/qualcomm/sc7280/include/soc/qspi.h M src/soc/qualcomm/sc7280/qspi.c 2 files changed, 9 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/47078/1 diff --git a/src/soc/qualcomm/sc7280/include/soc/qspi.h b/src/soc/qualcomm/sc7280/include/soc/qspi.h index 6c40e7e..570a7cb 100644 --- a/src/soc/qualcomm/sc7280/include/soc/qspi.h +++ b/src/soc/qualcomm/sc7280/include/soc/qspi.h @@ -6,6 +6,8 @@ #ifndef __SOC_QUALCOMM_SC7280_QSPI_H__ #define __SOC_QUALCOMM_SC7280_QSPI_H__ +#define QSPI_BASE 0x088DC000 + struct sc7280_qspi_regs { u32 mstr_cfg; u32 ahb_mstr_cfg; diff --git a/src/soc/qualcomm/sc7280/qspi.c b/src/soc/qualcomm/sc7280/qspi.c index a6837bc..3c627a5 100644 --- a/src/soc/qualcomm/sc7280/qspi.c +++ b/src/soc/qualcomm/sc7280/qspi.c @@ -7,7 +7,7 @@ #include <soc/addressmap.h> #include <soc/qspi.h> #include <soc/gpio.h> -#include <soc/clock.h> +//#include <soc/clock.h> #include <symbols.h> #include <assert.h> #include <gpio.h> @@ -136,6 +136,7 @@ return next; } +/* static void cs_change(enum cs_state state) { gpio_set(GPIO(15), state == CS_DEASSERT); @@ -154,6 +155,7 @@ gpio_configure(GPIO(14), GPIO14_FUNC_QSPI_CLK, GPIO_NO_PULL, GPIO_2MA, GPIO_OUTPUT_ENABLE); } +*/ static void queue_bounce_data(uint8_t *data, uint32_t data_bytes, enum qspi_mode data_mode, bool write) @@ -251,20 +253,20 @@ void quadspi_init(uint32_t hz) { assert(dcache_line_bytes() == CACHE_LINE_SIZE); - clock_configure_qspi(hz * 4); - configure_gpios(); +// clock_configure_qspi(hz * 4); +// configure_gpios(); reg_init(); } int sc7280_claim_bus(const struct spi_slave *slave) { - cs_change(CS_ASSERT); +// cs_change(CS_ASSERT); return 0; } void sc7280_release_bus(const struct spi_slave *slave) { - cs_change(CS_DEASSERT); +// cs_change(CS_DEASSERT); } static int xfer(enum qspi_mode mode, const void *dout, size_t out_bytes, -- To view, visit https://review.coreboot.org/c/coreboot/+/47078 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I148a7bd7910a6d23cbec354fe88b35644a8716bf Gerrit-Change-Number: 47078 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: trogdor: report hardware watchdog reset after reboot
by Ravi kumar (Code Review) 22 Mar '22

22 Mar '22

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/45070 ) Change subject: trogdor: report hardware watchdog reset after reboot ...................................................................... trogdor: report hardware watchdog reset after reboot Change-Id: I57ece39ff3d49f2bab259cbd92ab039a49323119 Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I3d03d775634e4f50f83b0e8e16b106b1183ec46b --- M src/soc/qualcomm/sc7180/soc.c 1 file changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/45070/1 diff --git a/src/soc/qualcomm/sc7180/soc.c b/src/soc/qualcomm/sc7180/soc.c index 74f0868..b529bf6 100644 --- a/src/soc/qualcomm/sc7180/soc.c +++ b/src/soc/qualcomm/sc7180/soc.c @@ -6,6 +6,11 @@ #include <soc/mmu_common.h> #include <soc/symbols.h> #include <soc/aop.h> +#include <elog.h> +#include <console/console.h> + +#define AOSS_CC_RESET_STATUS 0x0C2F0020 +#define WDOG_RESET_BIT_MASK 0x1 static void soc_read_resources(struct device *dev) { @@ -19,6 +24,14 @@ static void soc_init(struct device *dev) { + volatile unsigned int aoss = *(unsigned int *)AOSS_CC_RESET_STATUS; + + printk(BIOS_INFO, "\nSOC: AOSS_CC_RESET_STATUS : %x\n", aoss & WDOG_RESET_BIT_MASK); + printk(BIOS_INFO, "AOSS_CC_RESET_STATUS[%x]..[%x]\n", AOSS_CC_RESET_STATUS, aoss); + + if(aoss & WDOG_RESET_BIT_MASK) + elog_add_event(ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED); + aop_fw_load_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/45070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d03d775634e4f50f83b0e8e16b106b1183ec46b Gerrit-Change-Number: 45070 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: HACK Fix for rebase build error HACK
by Ravi Kumar Bokka (Code Review) 22 Mar '22

22 Mar '22

Ravi Kumar Bokka has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/57812 ) Change subject: HACK Fix for rebase build error HACK ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/57812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf43d1a3a277e6c4f5b8e3eff5db181e278015d0 Gerrit-Change-Number: 57812 Gerrit-PatchSet: 4 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: abandon

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022