coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi, Eric Lai. Varshit B Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Patch Set 3: (1 comment) File src/drivers/intel/dptf/dptf.c: https://review.coreboot.org/c/coreboot/+/62944/comment/39b4d06a_91fd5ff7 PS2, Line 387: acpigen_write_device_end(); /* TPWR Power Participant Device */ > oh true. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:15:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: RFC: Add initial support for the bootguarded framework tigerlake lapt...
by build bot (Jenkins) (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Felix Singer, Jonathan Neuschäfer, Christoph Pomaska. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62569 ) Change subject: RFC: Add initial support for the bootguarded framework tigerlake laptop (hx20) ...................................................................... Patch Set 5: Verified+1 (5 comments) File src/mainboard/framework/tgl_laptop/Kconfig: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144420): https://review.coreboot.org/c/coreboot/+/62569/comment/de050c34_fa2e5fd5 PS5, Line 1: if BOARD_FRAMWORK_TGL 'FRAMWORK' may be misspelled - perhaps 'FRAMEWORK'? File src/mainboard/framework/tgl_laptop/Kconfig.name: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144420): https://review.coreboot.org/c/coreboot/+/62569/comment/fbf7aeb7_e61dd014 PS5, Line 1: config BOARD_FRAMWORK_TGL 'FRAMWORK' may be misspelled - perhaps 'FRAMEWORK'? File src/mainboard/framework/tgl_laptop/romstage.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144420): https://review.coreboot.org/c/coreboot/+/62569/comment/e6336293_c7bf5b2a PS5, Line 17: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144420): https://review.coreboot.org/c/coreboot/+/62569/comment/60fb1cd5_7daedcaa PS5, Line 19: { that open brace { should be on the previous line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144420): https://review.coreboot.org/c/coreboot/+/62569/comment/ad398ac1_66bd402e PS5, Line 23: { that open brace { should be on the previous line -- To view, visit https://review.coreboot.org/c/coreboot/+/62569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaf215cccae8836d691392e3e584f49f675f8456 Gerrit-Change-Number: 62569 Gerrit-PatchSet: 5 Gerrit-Owner: Mimoja <coreboot(a)mimoja.de> Gerrit-Reviewer: Christoph Pomaska <github(a)slrie.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Christoph Pomaska <github(a)slrie.de> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:09:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Felix Singer, Jeff Daly, Mariusz Szafrański, Jonathan Zhang, Arthur Heymans, Michael Niewöhner, Andrey Petrov, Patrick Rudolph, Nico Huber, Anjaneya "Reddy" Chagam, Johnny Lin, Tim Wawrzynczak, Suresh Bellampalli, Christian Walter, Vanessa Eusebio, Lean Sheng Tan, Michal Motyl, Werner Zeh, Tim Chu. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62064 ) Change subject: soc/intel: Move `pmc_clear_pmcon_sts()` into IA common code ...................................................................... Patch Set 13: (1 comment) Patchset: PS13: Ping! -- To view, visit https://review.coreboot.org/c/coreboot/+/62064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d15f421c128630f928a1b6a7e2840056d68d7b1 Gerrit-Change-Number: 62064 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 07:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: ec/google: Add PSRC and PBOK method
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Hello build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62945 to look at the new patch set (#3). Change subject: ec/google: Add PSRC and PBOK method ...................................................................... ec/google: Add PSRC and PBOK method As per Intel Dynamic Tuning revision 1.3.13 add support for PSRC and PBOK under \_SB.DPTF.TPWR device ec_fill_dptf_helpers() is used to generate all the helper function that DPTF requires. BUG=b:205928013 TEST=Buil, boot brya0 and dump SSDT to check methods Scope (\_SB.DPTF.TPWR) { Method (PSRC, 0, Serialized) { Local0 = \_SB.PCI0.LPCB.EC0.PWRT /* External reference */ Return ((Local0 && 0x0F)) } Method (PBOK, 1, Serialized) { Local0 = Arg0 Local0 &= 0x0F \_SB.PCI0.LPCB.EC0.PBOK = Local0 } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 --- M src/ec/google/chromeec/ec_dptf_helpers.c 1 file changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/62945/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62945 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia536a9e1528f6e415247eca9ed2b0b685eb73196 Gerrit-Change-Number: 62945 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Varshit B Pandya, Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Hello Lance Zhao, build bot (Jenkins), Subrata Banik, Rizwan Qureshi, Tim Wawrzynczak, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62944 to look at the new patch set (#3). Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... drivers/intel/dptf: Add support for Power participant As per Intel Dynamic Tuning revision 1.3.13 add support for TPWR device under \_SB.DPTF BUG=b:205928013 TEST=Build, boot brya0 and dump SSDT to check TPWR device Device (TPWR) { Name (_HID, "") // _HID: Hardware ID Name (_UID, "TPWR") // _UID: Unique ID Name (_STR, "Power Participant") // _STR: Description String Name (PTYP, 0x11) Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 --- M src/acpi/acpigen_dptf.c M src/drivers/intel/dptf/Kconfig M src/drivers/intel/dptf/dptf.c M src/drivers/intel/dptf/dptf.h M src/include/acpi/acpigen_dptf.h 5 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/62944/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/i2c/sx9360: Add pre-charge resistance setting
by Gwendal Grignou (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Paul Menzel. Gwendal Grignou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62842 ) Change subject: driver/i2c/sx9360: Add pre-charge resistance setting ...................................................................... Patch Set 3: (1 comment) File src/drivers/i2c/sx9360/chip.h: https://review.coreboot.org/c/coreboot/+/62842/comment/65ee4313_82348cec PS1, Line 40: input_precharge_resistor > … also include the unit to the variable name? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I197b88d92784015b94c836dc128bacf3f1ef5b62 Gerrit-Change-Number: 62842 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 06:49:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: driver/i2c/sx9360: Add pre-charge resistance setting
by Gwendal Grignou (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Gwendal Grignou. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62842 to look at the new patch set (#3). Change subject: driver/i2c/sx9360: Add pre-charge resistance setting ...................................................................... driver/i2c/sx9360: Add pre-charge resistance setting Kernel driver supports ability to set the pre-charge resistance, add entry in the coreboot driver. [https://patchwork.ozlabs.org/project/devicetree-bindings/patch/202203220625…] Tested on bugzyy, check register 0x21 is configured properly. Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I197b88d92784015b94c836dc128bacf3f1ef5b62 --- M src/drivers/i2c/sx9360/chip.h M src/drivers/i2c/sx9360/sx9360.c 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62842/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I197b88d92784015b94c836dc128bacf3f1ef5b62 Gerrit-Change-Number: 62842 Gerrit-PatchSet: 3 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/i2c/sx9360: Add pre-charge resistance setting
by Gwendal Grignou (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Gwendal Grignou. Hello build bot (Jenkins), Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62842 to look at the new patch set (#2). Change subject: driver/i2c/sx9360: Add pre-charge resistance setting ...................................................................... driver/i2c/sx9360: Add pre-charge resistance setting Kernel driver supports ability to set the pre-charge resistance, add entry in the coreboot driver. [https://patchwork.ozlabs.org/project/devicetree-bindings/patch/202203220625…] Tested on bugzyy, check register 0x21 is configured properly. Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I197b88d92784015b94c836dc128bacf3f1ef5b62 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M src/drivers/i2c/sx9360/chip.h M src/drivers/i2c/sx9360/sx9360.c 5 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62842/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I197b88d92784015b94c836dc128bacf3f1ef5b62 Gerrit-Change-Number: 62842 Gerrit-PatchSet: 2 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: driver/i2c/sx9360: Add pre-charge resistance setting
by Gwendal Grignou (Code Review) 22 Mar '22

22 Mar '22

Gwendal Grignou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62981 ) Change subject: driver/i2c/sx9360: Add pre-charge resistance setting ...................................................................... Abandoned Invalid git push. -- To view, visit https://review.coreboot.org/c/coreboot/+/62981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef1ab3688402d1162be2c3c44ebd9ec8862a287 Gerrit-Change-Number: 62981 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: driver/i2c/sx9360: Add pre-charge resistance setting
by Gwendal Grignou (Code Review) 22 Mar '22

22 Mar '22

Gwendal Grignou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62981 ) Change subject: driver/i2c/sx9360: Add pre-charge resistance setting ...................................................................... driver/i2c/sx9360: Add pre-charge resistance setting Kernel driver supports ability to set the pre-charge resistance, add entry in the coreboot driver. [https://patchwork.ozlabs.org/project/devicetree-bindings/patch/202203220625…] Tested on bugzyy, check register 0x21 is configured properly. Signed-off-by: Gwendal Grignou <gwendal(a)chromium.org> Change-Id: I9ef1ab3688402d1162be2c3c44ebd9ec8862a287 --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M src/drivers/i2c/sx9360/chip.h M src/drivers/i2c/sx9360/sx9360.c 5 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62981/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 9e8f457..539d31a 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 9e8f457edcc359552a5d0113568a2d1670009178 +Subproject commit 539d31ab9ea89084fa5edf7cc9ac3122786d5454 diff --git a/3rdparty/blobs b/3rdparty/blobs index f14575c..fe7040a 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f14575cb9924b051cedfb4c1f62e3640b25f9dbd +Subproject commit fe7040a278642dc3d28e20eb7e7866cb6e2ac2ac diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 115c3e4..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 115c3e4cdad6a9d84bf06e066162c5c546a9d2c3 +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/src/drivers/i2c/sx9360/chip.h b/src/drivers/i2c/sx9360/chip.h index 397ea3f..4dcc722 100644 --- a/src/drivers/i2c/sx9360/chip.h +++ b/src/drivers/i2c/sx9360/chip.h @@ -35,6 +35,9 @@ /* Capacitance measure resolution. Driver default: 128. */ uint32_t resolution; + + /* Precharge input resistance. Driver default: 0. */ + uint32_t input_precharge_resistor_kohms; }; #endif /* __DRIVERS_I2C_SX9360_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9360/sx9360.c b/src/drivers/i2c/sx9360/sx9360.c index 9ea4c8b..035bfd5 100644 --- a/src/drivers/i2c/sx9360/sx9360.c +++ b/src/drivers/i2c/sx9360/sx9360.c @@ -63,6 +63,8 @@ config->avg_pos_strength); acpi_dp_add_integer(dsd, "semtech,resolution", config->resolution); + acpi_dp_add_integer(dsd, "semtech,input-precharge-resistor-kohms", + config->input_precharge_resistor_kohms); acpi_dp_write(dsd); -- To view, visit https://review.coreboot.org/c/coreboot/+/62981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ef1ab3688402d1162be2c3c44ebd9ec8862a287 Gerrit-Change-Number: 62981 Gerrit-PatchSet: 1 Gerrit-Owner: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022