coreboot-gerrit March 2022

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Yu-Ping Wu (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 22: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 22 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 06:36:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Yu-Ping Wu (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Xixi Chen. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 27 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 06:29:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Xixi Chen (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62065 to look at the new patch set (#22). Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... src/mediatek/mt8186: Implement sdram_size() to get real dram size Originally, dram size is hard-coded to 4GB by default. To support different dram size, calculate it from the mem chip info stored in CBMEM. BUG=b:206014043 TEST=Output "dram size: 0x100000000" on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 --- M src/soc/mediatek/mt8186/emi.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62065/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 22 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Xixi Chen (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 21: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62065/comment/415bed8a_d7bfe249 PS20, Line 9: set to 4GB by default > hard-coded to 4GB Done File src/soc/mediatek/mt8186/emi.c: https://review.coreboot.org/c/coreboot/+/62065/comment/e3a0ae47_777550bb PS20, Line 28: channel = (void *)((uintptr_t)mc + sizeof(*mc)); > Please fix this. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 21 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 06:08:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Xixi Chen (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Yu-Ping Wu. Xixi Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... Patch Set 27: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61334/comment/7cf893f6_c8178a63 PS26, Line 9: payloads > ramstage or payloads Done File src/soc/mediatek/common/memory.c: https://review.coreboot.org/c/coreboot/+/61334/comment/62ed3ad8_da30871c PS26, Line 127: channel > mc->channel Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 27 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 06:07:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Xixi Chen (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62065 to look at the new patch set (#21). Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... src/mediatek/mt8186: Implement sdram_size() to get real dram size Originally, dram size is hard-coded to 4GB by default. To support different dram size, calculate it from the mem chip info stored in CBMEM. BUG=b:206014043 TEST=Output "dram size: 0x100000000" on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 --- M src/soc/mediatek/mt8186/emi.c 1 file changed, 20 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62065/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 21 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Xixi Chen (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Hung-Te Lin, Xi Chen, Paul Menzel, Julius Werner, Xixi Chen. Hello Xi Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61334 to look at the new patch set (#27). Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... soc/mediatek: Save dram info to cbmem Store dram info in cbmem for ramstage or payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 2 files changed, 49 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/61334/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 27 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update telemetry settings
by Kevin Chiu (Code Review) 22 Mar '22

22 Mar '22

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62980 ) Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings ...................................................................... mb/google/guybrush/var/nipperkin: update telemetry settings Update the two load line slope settings for the telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. VDD scale: 73331 -> 94623 VDD offset: 1893 -> 1847 SOC scale: 31955 -> 29904 SOC offset: 852 -> 756 BUG=b:217963719 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage pass AMD SDLE/Stardust test Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com> --- M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/62980/1 diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index 668c109..6d6285a 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -207,10 +207,10 @@ register "sustained_power_limit_mW" = "12000" register "thermctl_limit_degreeC" = "100" - register "telemetry_vddcrvddfull_scale_current_mA" = "73331" #mA - register "telemetry_vddcrvddoffset" = "1893" - register "telemetry_vddcrsocfull_scale_current_mA" = "31955" #mA - register "telemetry_vddcrsocoffset" = "852" + register "telemetry_vddcrvddfull_scale_current_mA" = "94623" #mA + register "telemetry_vddcrvddoffset" = "1847" + register "telemetry_vddcrsocfull_scale_current_mA" = "29904" #mA + register "telemetry_vddcrsocoffset" = "756" # Enable STT support register "stt_control" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/62980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Gerrit-Change-Number: 62980 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brask/variants/moli: init overridetree for moli
by Raihow Shi (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak. Raihow Shi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62321 ) Change subject: mb/google/brask/variants/moli: init overridetree for moli ...................................................................... Patch Set 32: (1 comment) File src/mainboard/google/brya/variants/moli/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62321/comment/5d626b83_cae81996 PS30, Line 67: 5 using clk > `PCIe 6 using clk 5` done -- To view, visit https://review.coreboot.org/c/coreboot/+/62321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8829d4b39d48ae574eeccbfc62e79b671211ae2d Gerrit-Change-Number: 62321 Gerrit-PatchSet: 32 Gerrit-Owner: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Johnny Li <johnny_li(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Peter Chi <peter_chi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Will Tsai <will_tsai(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:56:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62973 ) Change subject: mb/google/brya/var/taeko: Disable GL9763e PCIE port L0s ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6ed790c833d1c01a30aed0fd09cac260a3837ead Gerrit-Change-Number: 62973 Gerrit-PatchSet: 4 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Peichao Wang <pwang12(a)lenovo.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 22 Mar 2022 05:44:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022