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Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
......................................................................
Patch Set 11: Code-Review+1
(3 comments)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62919/comment/cc92ada6_0c01f58b
PS11, Line 300: static unsigned int get_aspm_control(enum ASPM_control ctl)
nit: can you add a comment similar to the one above get_l1_substate_control()
suggestion:
```
/*
* Chip config parameter pcie_rp_aspm uses (UPD value + 1) because
* a UPD value of 0 for pcie_rp_aspm means disabled. In order to ensure
* that the mainboard setting does not disable ASPM incorrectly, chip
* config parameter values are offset by 1 with 0 meaning use FSP UPD default.
* get_aspm_control() ensures that the right UPD value is set in fsp_params.
* 0: Use FSP UPD default
* 1: Disable ASPM
* 2: L0s only
* 3: L1 only
* 4: L0s and L1
* 5: Auto configuration
*/
```
File src/soc/intel/common/block/include/intelblocks/pcie_rp.h:
https://review.coreboot.org/c/coreboot/+/62919/comment/7559894e_b834ade9
PS11, Line 63: ntrol PcieRpL1Substates;
:
`/* PCIe RP ASPM */`
https://review.coreboot.org/c/coreboot/+/62919/comment/cc424a04_679229f2
PS11, Line 65: PcieRpAspm
nit:
`pcie_rp_aspm`
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Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
......................................................................
Patch Set 11: Code-Review+2
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Change subject: soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62919/comment/3cef28a0_88ff353f
PS10, Line 7: mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
:
: Add ASPM parameter setting in Soc.
> soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config. […]
Update in latest patch.
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Change subject: mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
......................................................................
Patch Set 10:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62919/comment/899fbd70_0f84c919
PS10, Line 7: mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
:
: Add ASPM parameter setting in Soc.
soc/intel/{adl,common}: Add ASPM setting in pcie_rp_config.
This change provides config for devicetree to control ASPM per port
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Change subject: $top/Makefile.inc: Move common folder before other sibling ones
......................................................................
Patch Set 9:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62750/comment/23c6eca9_5ca9d143
PS3, Line 13: The duplicated "common" in the result string can be eliminated finally.
> So, sorry, are you saying that `-include` would somehow magically keep track of which files it has a […]
Done
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Change subject: mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
......................................................................
Patch Set 10:
(2 comments)
Patchset:
PS9:
> Please split the mainboard and SoC changes into 2 separate commits
Updated in latest patch.
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/62919/comment/fc735004_c9da4a41
PS9, Line 300: int
> nit: `unsigned int`
Updated in latest patch.
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Hello build bot (Jenkins), Peichao Wang, Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62919
to look at the new patch set (#10).
Change subject: mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
......................................................................
mb/google/brya/var/taeko: Add root port ASPM settiing in Soc.
Add ASPM parameter setting in Soc.
BUG=b:220079865
TEST=Build FW and run stress exceed 2500 cycles.
Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com>
Change-Id: I19b5f3dc8d95e153301d777492c921ce582ba988
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 21 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/62919/10
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Martin Roth, Marshall Dawson, Paul Menzel, Zheng Bao, Elyes Haouas, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: $top/Makefile.inc: Move common folder before other sibling ones
......................................................................
$top/Makefile.inc: Move common folder before other sibling ones
Putting
src/soc/*/common before src/soc/*/*, and
src/superio/common before src/superio/*,(which is already moved but
with duplicated folder "common")
can make the variables in
common Makefile get the expected value before they are used in other
subdirs.
The later "*" also contains "common", which needs to be eliminated by
"filter-out".
Then we can put some common variables from all the subdir Makefile.inc
to the common Makefile.inc to reduce code redundancy.
Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M Makefile.inc
1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/62750/9
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Change subject: [TEST] soc/intel/alderlake:set slopes,enable ER & RTH
......................................................................
Patch Set 1:
(9 comments)
File src/soc/intel/alderlake/fsp_params.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/bdcc9a79_5d0e1a36
PS1, Line 726: s_cfg->PchPmDisableEnergyReport = 0x0;
trailing whitespace
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/a06e2e26_5741d0e8
PS1, Line 727: s_cfg->RaceToHalt = 0x1;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/4ace51a9_85756b2c
PS1, Line 727: s_cfg->RaceToHalt = 0x1;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/954e0743_b7e223a9
PS1, Line 728: s_cfg->ImonSlope[0] = 143;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/52f24a15_a6c315b4
PS1, Line 728: s_cfg->ImonSlope[0] = 143;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/b29b6c93_3d54d01d
PS1, Line 729: s_cfg->ImonSlope[1] = 103;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/ffaa8bc8_83f22a71
PS1, Line 729: s_cfg->ImonSlope[1] = 103;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/831bb9a7_4d59e0ae
PS1, Line 730: s_cfg->VccInAuxImonSlope = 111;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144388):
https://review.coreboot.org/c/coreboot/+/62972/comment/4814a225_9efe43a1
PS1, Line 730: s_cfg->VccInAuxImonSlope = 111;
please, no spaces at the start of a line
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