coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62987 ) Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/alderlake/me.c: https://review.coreboot.org/c/coreboot/+/62987/comment/bb715907_915e9cef PS3, Line 179: assert > if you use `die()` you can at least get a message on the screen. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:46:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62986 ) Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/spi/spi.c: https://review.coreboot.org/c/coreboot/+/62986/comment/d4653120_dcd65e88 PS3, Line 53: #if ENV_RAMSTAGE > Is this required? This is not required. -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:46:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62987 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... soc/intel/alderlake: Log CSE RO write protection info for ADL The patch logs write protection information for Alder Lake platform. As part of write protection informaiton, coreboot logs status on CSE RO write protection and range. Also, triggers assert if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 --- M src/soc/intel/alderlake/me.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62986 to look at the new patch set (#4). Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... soc/intel/common: Add APIs to check CSE's write protection info The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a Intel MFIT XML configuration. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b --- M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/spi/spi.c 2 files changed, 92 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/62986/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Move documentation license to main menu
by Paul Menzel (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Felix Singer, Nico Huber, Patrick Georgi, Angel Pons, Michael Niewöhner, Patrick Rudolph. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62767 ) Change subject: Documentation: Move documentation license to main menu ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8bfc4f52da8a93d78a62e3a68fd6f1dc8ae4d335 Gerrit-Change-Number: 62767 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:44:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63009/comment/e3f1a669_8e8b0861 PS2, Line 43: select FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Can we depend CONFIG_CONSOLE_SERIAL or CONFIG_UART_DEBUG? I think the normal image, we don't need to know FSP log. -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:30:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/moonbuggy: Update GPIOs
by Pablo Ceballos (Code Review) 23 Mar '22

23 Mar '22

Pablo Ceballos has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63014 ) Change subject: mb/google/hatch/moonbuggy: Update GPIOs ...................................................................... mb/google/hatch/moonbuggy: Update GPIOs Implement the GPIOs that have been changed from genesis. - Connect scaler UART on pins C12/C13 - Connect the HDMI redriver I2C on C18/C19 - Connect the iMX8 signals on D1/D2/D3/D21/D22 - Connect the EC interrupt on D14 (same as on scout) - Connect PCH_TYPEC_UPFB on E15 (same as on genesis) - Configure as not connected the following unused pins: D23, E11, E12, F11 -> F22, H0, H8, H9 BUG=b:200876872 TEST=moonbuggy boots Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Signed-off-by: Pablo Ceballos <pceballos(a)google.com> --- M src/mainboard/google/hatch/variants/moonbuggy/gpio.c M src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h M src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb 3 files changed, 59 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/63014/1 diff --git a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c index ba75fb7..d8f3920 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/gpio.c +++ b/src/mainboard/google/hatch/variants/moonbuggy/gpio.c @@ -33,65 +33,79 @@ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* C1 : SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - /* C3 : PCH_MBCLK1_R (i350) */ + /* C3 : PCH_MBCLK1_R (i350) */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), - /* C4 : PCH_MBDAT1_R (i350) */ + /* C4 : PCH_MBDAT1_R (i350) */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), - /* C6: M2_WLAN_WAKE_ODL */ + /* C6 : M2_WLAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE), /* C7 : LAN_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE), /* C10 : PCH_PCON_RST_ODL */ PAD_CFG_GPO(GPP_C10, 1, DEEP), - /* C11 : PCH_PCON_PDB_ODL */ + /* C11 : PCH_PCON1_PDB_ODL */ PAD_CFG_GPO(GPP_C11, 1, DEEP), - /* C15 : WLAN_OFF_L */ + /* C12 : PCH_UART1_RX_ADB_TX */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* C13 : PCH_UART1_TX_ADB_RX */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* C15 : WLAN_OFF_L */ PAD_CFG_GPO(GPP_C15, 1, DEEP), + /* C16 : PCH_I2C_RFU_SDA (NC) */ + PAD_NC(GPP_C16, NONE), + /* C17 : PCH_I2C_RFU_SCL (NC) */ + PAD_NC(GPP_C17, NONE), + /* C18 : EC_I2C_HDMI_RE_SCL */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : EC_12C_HDMI_RE_SDA */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* D1 : REC_MODE */ + PAD_CFG_GPO(GPP_D1, 1, DEEP), + /* D2 : DEV_MODE_CTRL */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + /* D3 : BOOT_IND */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D14 : EC_PCH_INT_L */ + PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT), + /* D21 : BOOT_SEL_N */ + PAD_CFG_GPO(GPP_D21, 1, DEEP), + /* D22 : QSPI_MR_N */ + PAD_CFG_GPO(GPP_D22, 1, DEEP), + /* D23 : Not connected */ + PAD_NC(GPP_D23, NONE), /* E2 : Not connected */ PAD_NC(GPP_E2, NONE), - /* E3 : TPU_RST_PIN40 */ + /* E3 : TPU_BOOT_DELAY_PIN40 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), - /* E7 : TPU_RST_PIN42 */ + /* E7 : TPU_BOOT_DELAY_PIN42 */ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* E9 : PU 10K to PP3300_SOC_A */ PAD_NC(GPP_E9, NONE), /* E10 : USB_A1_OC_ODL */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), + /* E11 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E11, NONE), + /* E12 : PU 10K to PP3300_SOC_A */ + PAD_NC(GPP_E12, NONE), + /* E15 : PCH_TYPEC_UPFB */ + PAD_CFG_GPI(GPP_E15, NONE, DEEP), - /* F11 : EMMC_CMD */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), - /* F12 : EMMC_DATA0 */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), - /* F13 : EMMC_DATA1 */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), - /* F14 : EMMC_DATA2 */ - PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), - /* F15 : EMMC_DATA3 */ - PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), - /* F16 : EMMC_DATA4 */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), - /* F17 : EMMC_DATA5 */ - PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), - /* F18 : EMMC_DATA6 */ - PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), - /* F19 : EMMC_DATA7 */ - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - /* F20 : EMMC_RCLK */ - PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), - /* F21 : EMMC_CLK */ - PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), - /* F22 : EMMC_RST_L */ - PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), - - /* H4: PCH_I2C_PCON_SDA */ + /* H0 : Not connected */ + PAD_NC(GPP_H0, NONE), + /* H4 : PCH_I2C_PCON_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* H5: PCH_I2C_PCON_SCL */ + /* H5 : PCH_I2C_PCON_SCL */ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* H6 : PCH_I2C_TPU_SDA */ + /* H6 : PCH_I2C_TPU_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* H7 : PCH_I2C_TPU_SCL */ + /* H7 : PCH_I2C_TPU_SCL */ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : Not connected */ + PAD_NC(GPP_H8, NONE), + /* H9 : Not connected */ + PAD_NC(GPP_H9, NONE), /* H22 : PWM_PP3300_BIOZZER */ PAD_CFG_GPO(GPP_H22, 0, DEEP), }; @@ -122,7 +136,7 @@ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 0, DEEP), - /* PCH_WP_OD */ + /* C20 : PCH_WP_OD */ PAD_CFG_GPI(GPP_C20, NONE, DEEP), /* C21 : H1_PCH_INT_ODL */ PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), @@ -130,9 +144,9 @@ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), - /* E1 : M2_SSD_PEDET */ + /* E1 : M2_SSD_PEDET */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), - /* E5 : SATA_DEVSLP1 */ + /* E5 : SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), }; diff --git a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h index 79a1410..9dd2434 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h +++ b/src/mainboard/google/hatch/variants/moonbuggy/include/variant/gpio.h @@ -5,4 +5,7 @@ #include <baseboard/gpio.h> +#undef EC_SYNC_IRQ +#define EC_SYNC_IRQ GPP_D14_IRQ + #endif diff --git a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb index dd83f4d..1049805 100644 --- a/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb +++ b/src/mainboard/google/hatch/variants/moonbuggy/overridetree.cb @@ -13,7 +13,7 @@ [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoPci, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" @@ -451,6 +451,8 @@ device pci 1d.5 on end # PCI Root Port 14 (non-root) device pci 1d.6 on end # PCI Root Port 15 (non-root) device pci 1d.7 on end # PCI Root Port 16 (non-root) + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 device pci 1e.3 off end # GSPI #1 end -- To view, visit https://review.coreboot.org/c/coreboot/+/63014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Gerrit-Change-Number: 63014 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Ceballos <pceballos(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/i2c/tpm: Add workaround for Ti50
by Kangheui Won (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak, Christian Walter, Eric Lai. Kangheui Won has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63011 ) Change subject: drivers/i2c/tpm: Add workaround for Ti50 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:06:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Amanda Hwang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 05:04:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Enable dynamic debug capability for brya family
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Paul Menzel, Tim Wawrzynczak, Patrick Rudolph. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61381 ) Change subject: mb/google/brya: Enable dynamic debug capability for brya family ...................................................................... Patch Set 16: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61381/comment/86b6e73e_72b8fd24 PS16, Line 13: TEST= Verified the CSE firmware update functionality on Brya > What command can be used to verify the debug capability? We can't verify debug capability alone unless we test specific feature (like CSE Firmware Update) with the feature. The order of patches have been changed. So, the commit message has to be re-written. -- To view, visit https://review.coreboot.org/c/coreboot/+/61381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b0e0bb4392d3fbdb50577d3644491ab90a33c3 Gerrit-Change-Number: 61381 Gerrit-PatchSet: 16 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 04:41:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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coreboot-gerrit March 2022