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Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> if this won't increase boot time, it's fine.
Writing console to memory when caching is properly set up should have a negligible boot time impact.
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
Patch Set 8: Code-Review+1
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
Patch Set 8:
(1 comment)
File src/mainboard/google/brya/variants/banshee/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/62804/comment/aaf5c753_796cdc1c
PS5, Line 328: register "privacy_gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_F19)"
> Changing the privacy GPIO polarity is unrelated to the mic mute switch, it should go in a separate C […]
Removed it.
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Hello build bot (Jenkins), John Su, YH Lin, Dtrain Hsu, Ian Feng, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Amanda Hwang, Ricky Chang,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62804
to look at the new patch set (#8).
Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
......................................................................
mb/google/brya/var/banshee: Add mic mute switch setting
Using the GPP_F22 as mic mute switch based on the latest schematic.
BUG=b:223737606, b:216110896
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
The mic_mute event is changed when the mic_mute GPIO pin is switched.
Event: time 1647939954.639995, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 0
Event: time 1647939954.639995, -------------- SYN_REPORT ------------
Event: time 1647939954.648152, type 5 (EV_SW), code 14 (SW_MUTE_DEVICE), value 1
Event: time 1647939954.648152, -------------- SYN_REPORT ------------
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
Change-Id: I6f7176afbd64f7c080f02369f195043a2df88e5d
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/banshee/gpio.c
M src/mainboard/google/brya/variants/banshee/overridetree.cb
3 files changed, 14 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/62804/8
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Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
if this won't increase boot time, it's fine.
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Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/63009/comment/4719c5f3_3c879a94
PS2, Line 43: select FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT
> Can we depend CONFIG_CONSOLE_SERIAL or CONFIG_UART_DEBUG? I think the normal image, we don't need to know FSP log.
Isn't the whole point to be console agnostic and let coreboot do the console printing wherever it seems fit? Even without series I still see value in printing output to for instance the cbmem console.
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Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
......................................................................
Patch Set 2: Code-Review+2
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Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Because mrc.bin already had this I was surprised to find out this was not a feature with FSP. Great stuff. +3
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