coreboot-gerrit March 2022

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Hung-Te Lin (Code Review) 23 Mar '22

23 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... src/mediatek/mt8186: Implement sdram_size() to get real dram size Originally, dram size is hard-coded to 4GB by default. To support different dram size, calculate it from the mem chip info stored in CBMEM. BUG=b:206014043 TEST=Output "dram size: 0x100000000" on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62065 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/mt8186/emi.c 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/mt8186/emi.c b/src/soc/mediatek/mt8186/emi.c index 48a7b3e..6e25441 100644 --- a/src/soc/mediatek/mt8186/emi.c +++ b/src/soc/mediatek/mt8186/emi.c @@ -5,11 +5,30 @@ * Chapter number: 4.8 */ +#include <assert.h> +#include <cbmem.h> +#include <commonlib/bsd/mem_chip_info.h> #include <soc/emi.h> size_t sdram_size(void) { - return (size_t)4 * GiB; + const struct mem_chip_info *mc; + size_t size = 0; + + if (ENV_ROMSTAGE) { + size = mtk_dram_size(); + printk(BIOS_INFO, "dram size (romstage): %#lx\n", size); + return size; + } + + mc = cbmem_find(CBMEM_ID_MEM_CHIP_INFO); + assert(mc); + + for (unsigned int i = 0; i < mc->num_channels; ++i) + size += mc->channel[i].density; + + printk(BIOS_INFO, "dram size: %#lx\n", size); + return size; } void mt_set_emi(struct dramc_param *dparam) -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 23 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek: Save dram info to cbmem
by Hung-Te Lin (Code Review) 23 Mar '22

23 Mar '22

Hung-Te Lin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61334 ) Change subject: soc/mediatek: Save dram info to cbmem ...................................................................... soc/mediatek: Save dram info to cbmem Store dram info in cbmem for ramstage or payloads to use. BUG=b:206014043 TEST=Build pass on Kingler Signed-off-by: Xi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Reviewed-on: https://review.coreboot.org/c/coreboot/+/61334 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 2 files changed, 49 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h index 60206d8..0070ec1 100644 --- a/src/soc/mediatek/common/include/soc/emi.h +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -6,6 +6,7 @@ #include <soc/dramc_param.h> size_t sdram_size(void); +size_t mtk_dram_size(void); void mt_set_emi(struct dramc_param *dparam); void mt_mem_init(struct dramc_param *dparam); void mtk_dram_init(void); diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 3ca3611..2e460ae 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -3,6 +3,8 @@ #include <assert.h> #include <bootmode.h> #include <cbfs.h> +#include <cbmem.h> +#include <commonlib/bsd/mem_chip_info.h> #include <console/console.h> #include <soc/dramc_common.h> #include <ip_checksum.h> @@ -23,6 +25,8 @@ const char *get_dram_geometry_str(u32 ddr_geometry); const char *get_dram_type_str(u32 ddr_type); +static const struct ddr_base_info *curr_ddr_info; + static int mt_mem_test(const struct dramc_data *dparam) { if (CONFIG(MEMORY_TEST)) { @@ -96,6 +100,49 @@ return s; } +size_t mtk_dram_size(void) +{ + size_t size = 0; + + if (!curr_ddr_info) + return 0; + for (unsigned int i = 0; i < RANK_MAX; ++i) + size += curr_ddr_info->mrr_info.mr8_density[i]; + return size; +} + +static void fill_dram_info(struct mem_chip_info *mc, const struct ddr_base_info *ddr) +{ + unsigned int i; + size_t size; + + mc->type = MEM_CHIP_LPDDR4X; + mc->num_channels = CHANNEL_MAX; + size = mtk_dram_size(); + assert(size); + + for (i = 0; i < mc->num_channels; ++i) { + mc->channel[i].density = size / mc->num_channels; + mc->channel[i].io_width = DQ_DATA_WIDTH_LP4; + mc->channel[i].manufacturer_id = ddr->mrr_info.mr5_vendor_id; + mc->channel[i].revision_id[0] = ddr->mrr_info.mr6_revision_id; + mc->channel[i].revision_id[1] = ddr->mrr_info.mr7_revision_id; + } +} + +static void add_mem_chip_info(int unused) +{ + struct mem_chip_info *mc; + size_t size; + + size = sizeof(*mc) + sizeof(struct mem_chip_channel) * CHANNEL_MAX; + mc = cbmem_add(CBMEM_ID_MEM_CHIP_INFO, size); + assert(mc); + + fill_dram_info(mc, curr_ddr_info); +} +ROMSTAGE_CBMEM_INIT_HOOK(add_mem_chip_info); + static int run_dram_blob(struct dramc_param *dparam) { /* Load and run the provided blob for full-calibration if available */ @@ -261,5 +308,6 @@ /* dramc_param is too large to fit in stack. */ static struct dramc_param dramc_parameter; mt_mem_init(&dramc_parameter); + curr_ddr_info = &dramc_parameter.dramc_datas.ddr_info; mtk_mmu_after_dram(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/61334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I195187c0c757a43bb6d2c57c8f303249f2a7995a Gerrit-Change-Number: 61334 Gerrit-PatchSet: 28 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Michał Żygowski (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Krystian Hebel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62211 ) Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... Patch Set 3: (3 comments) File src/mainboard/dell/snb_ivb_workstations/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62211/comment/0f29af39_7fc29dee PS2, Line 17: 4 > SlotLengthLong This file was supposed to be moved to variants/baseboard and I forgot to remove it. File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62211/comment/7dc5dd64_3b946d17 PS2, Line 16: 4 > SlotLengthLong Done https://review.coreboot.org/c/coreboot/+/62211/comment/60aea0ba_be4efc11 PS2, Line 53: device pci 1d.0 off end # USB2 EHCI #1 > Probably by accident, when I was disabling all PCIe ports. Good catch. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 11:28:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Michał Żygowski (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Krystian Hebel. Hello build bot (Jenkins), Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62211 to look at the new patch set (#3). Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... mb/dell: Convert OptiPlex 9010 into directory with variants New boards like Dell Precision T1650 will be added as variants, in subsequent commit. They share most of the code, except some EC initialization tables, PCIe port configuration and subsystem ID. Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 --- D src/mainboard/dell/optiplex_9010/Kconfig.name R src/mainboard/dell/snb_ivb_workstations/Kconfig A src/mainboard/dell/snb_ivb_workstations/Kconfig.name R src/mainboard/dell/snb_ivb_workstations/Makefile.inc R src/mainboard/dell/snb_ivb_workstations/acpi/ec.asl R src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl R src/mainboard/dell/snb_ivb_workstations/acpi/superio.asl R src/mainboard/dell/snb_ivb_workstations/board_info.txt R src/mainboard/dell/snb_ivb_workstations/cmos.default R src/mainboard/dell/snb_ivb_workstations/cmos.layout R src/mainboard/dell/snb_ivb_workstations/dsdt.asl R src/mainboard/dell/snb_ivb_workstations/early_init.c R src/mainboard/dell/snb_ivb_workstations/gma-mainboard.ads R src/mainboard/dell/snb_ivb_workstations/gpio.c C src/mainboard/dell/snb_ivb_workstations/hda_verb.c R src/mainboard/dell/snb_ivb_workstations/mainboard.c R src/mainboard/dell/snb_ivb_workstations/romstage.c R src/mainboard/dell/snb_ivb_workstations/sch5545_ec.c R src/mainboard/dell/snb_ivb_workstations/sch5545_ec_early.c R src/mainboard/dell/snb_ivb_workstations/smihandler.c R src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb R src/mainboard/dell/snb_ivb_workstations/variants/baseboard/include/baseboard/sch5545_ec.h R src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/data.vbt R src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/hda_verb.c A src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/include/variant/sch5545_ec_tables.h A src/mainboard/dell/snb_ivb_workstations/variants/optiplex_9010_sff/overridetree.cb 26 files changed, 317 insertions(+), 268 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/62211/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya/variants/crota: init overridetree for crota
by Terry Chen (Code Review) 23 Mar '22

23 Mar '22

Terry Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63022 ) Change subject: mb/google/brya/variants/crota: init overridetree for crota ...................................................................... mb/google/brya/variants/crota: init overridetree for crota init overridetree.cb based on the schematic bernadino 14 adl-p 20220112.pdf BUG=b:226315394 Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c --- M src/mainboard/google/brya/variants/crota/overridetree.cb 1 file changed, 310 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63022/1 diff --git a/src/mainboard/google/brya/variants/crota/overridetree.cb b/src/mainboard/google/brya/variants/crota/overridetree.cb index 4f2c04a..c4cca99 100644 --- a/src/mainboard/google/brya/variants/crota/overridetree.cb +++ b/src/mainboard/google/brya/variants/crota/overridetree.cb @@ -1,6 +1,314 @@ +fw_config + field MB_SD 0 1 + option SD_ABSENT 0 + option SD_GL9750 1 + end + field KB_BL 3 3 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field AUDIO 4 6 + option AUDIO_UNKNOWN 0 + ption MAX98360_CS42L42 1 + end + field DB_LTE 7 8 + option LTE_ABSENT 0 + option LTE_USB 1 + end +end + chip soc/intel/alderlake - device domain 0 on - end + # Acoustic settings + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | Fingerprint MCU | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C2 | | + #| I2C3 | Touchscreen | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 650, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable USB2_C1 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2_C4 + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2_C6 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Disable USB2_C8 + register "usb3_ports[0]" = "USB3_PORT_EMPTY" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + + device domain 0 on + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref pcie_rp3 on + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" + register "srcclk_pin" = "1" + device generic 0 alias emmc_rtd3 on end + end + # Enable PCIe-to-eMMC bridge PCIE 3 using clk 1 + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE3 BH799BB + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port3 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp6 off end #PCIE6 WWAN + device ref pcie_rp8 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" + register "srcclk_pin" = "3" + device generic 0 on end + end + end #PCIE8 SD card + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 1 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 1, + .clk_src = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref i2c0 on + chip drivers/i2c/cs42l42 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A23_IRQ)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B13)" + register "ts_inv" = "true" + register "ts_dbnc_rise" = "RISE_DEB_1000_MS" + register "ts_dbnc_fall" = "FALL_DEB_0_MS" + register "btn_det_init_dbnce" = "100" + register "btn_det_event_dbnce" = "10" + register "bias_lvls[0]" = "15" + register "bias_lvls[1]" = "8" + register "bias_lvls[2]" = "4" + register "bias_lvls[3]" = "1" + register "hs_bias_ramp_rate" = "HSBIAS_RAMP_SLOW" + register "hs_bias_sense_disable" = "true" + device i2c 48 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end + device ref i2c3 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9050"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" + register "generic.reset_delay_ms" = "300" + register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 0x10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "wake" = "GPE0_DW2_14" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""GXTP7288"" + register "generic.desc" = ""Goodix Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 2c on end + end + end + device ref hda on + chip drivers/generic/max98357a + register "hid" = ""MX98360A"" + register "sdmode_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A11)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + device spi 0 on end + end # FPMCU + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/63022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibca9d93a81469730e472a645c607a97a624e9a1c Gerrit-Change-Number: 63022 Gerrit-PatchSet: 1 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Michał Żygowski (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Krystian Hebel. Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62211 ) Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... Patch Set 2: (1 comment) File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62211/comment/510e743a_f05e3d26 PS2, Line 53: device pci 1d.0 off end # USB2 EHCI #1 > This was previously 'on', and it isn't turned back on in overridetree. […] Probably by accident, when I was disabling all PCIe ports. Good catch. -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 11:13:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Krystian Hebel (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Michał Żygowski. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62211 ) Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... Patch Set 2: (3 comments) File src/mainboard/dell/snb_ivb_workstations/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62211/comment/0965be56_346e44ef PS2, Line 17: 4 SlotLengthLong File src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb: https://review.coreboot.org/c/coreboot/+/62211/comment/28cd8a17_d990c364 PS2, Line 16: 4 SlotLengthLong https://review.coreboot.org/c/coreboot/+/62211/comment/0ae61890_0c66bfb0 PS2, Line 53: device pci 1d.0 off end # USB2 EHCI #1 This was previously 'on', and it isn't turned back on in overridetree.cb, why? -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 11:02:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs
by Krystian Hebel (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Michał Żygowski, Martin L Roth. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62210 ) Change subject: mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44 Gerrit-Change-Number: 62210 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 10:11:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: src/mediatek/mt8186: Implement sdram_size() to get real dram size
by Rex-BC Chen (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Hung-Te Lin, Xixi Chen. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62065 ) Change subject: src/mediatek/mt8186: Implement sdram_size() to get real dram size ...................................................................... Patch Set 22: (1 comment) Patchset: PS22: @hung-te, Can we merge these dram series? Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/62065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I017e9d1a2d6e26f1fc21b67b5962dfb5c6ade8a5 Gerrit-Change-Number: 62065 Gerrit-PatchSet: 22 Gerrit-Owner: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xixi Chen <xixi.chen(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 10:10:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/denverton_ns: Lock BIOS_CONTROL with EISS unset
by Jeff Daly (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Vanessa Eusebio, Kyösti Mälkki, Patrick Rudolph. Jeff Daly has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61145 ) Change subject: soc/intel/denverton_ns: Lock BIOS_CONTROL with EISS unset ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: just a follow up, i made the case to Intel that the latest version of FSP with the ability to control this setting from coreboot be released and they agreed they will do it mid Q2 this year. -- To view, visit https://review.coreboot.org/c/coreboot/+/61145 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9aaabd8e911ae87673be53b5f8f713099d6f2d0 Gerrit-Change-Number: 61145 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 09:56:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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