coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek: Add mtk_early_init for passing data across sessions
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Hung-Te Lin. Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63019 ) Change subject: soc/mediatek: Add mtk_early_init for passing data across sessions ...................................................................... soc/mediatek: Add mtk_early_init for passing data across sessions Passing pcie timestamp from bootblock stage to ram stage, it can be used for other modules if they needs to passing data across sessions. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a --- M src/soc/mediatek/common/Kconfig A src/soc/mediatek/common/early_init.c A src/soc/mediatek/common/include/soc/early_init.h 3 files changed, 73 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63019/1 diff --git a/src/soc/mediatek/common/Kconfig b/src/soc/mediatek/common/Kconfig index cd3b2a2..dd018ec 100644 --- a/src/soc/mediatek/common/Kconfig +++ b/src/soc/mediatek/common/Kconfig @@ -50,4 +50,8 @@ and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM to store logs of DFD. +config MEDIATEK_EARLY_INIT + bool + help + This option allows passing data across sessions. endif diff --git a/src/soc/mediatek/common/early_init.c b/src/soc/mediatek/common/early_init.c new file mode 100644 index 0000000..fee8f61 --- /dev/null +++ b/src/soc/mediatek/common/early_init.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <soc/early_init.h> +#include <stdlib.h> +#include <string.h> +#include <timer.h> + +static struct mtk_early_init *mtk_find_early_init(void) +{ + assert(sizeof(struct mtk_early_init) <= REGION_SIZE(mtk_early_init)); + return (struct mtk_early_init *)_mtk_early_init; +} + +void mtk_clear_early_init(void) +{ + struct mtk_early_init *init = mtk_find_early_init(); + + if (!init) + return; + + memset(init, 0, sizeof(*init)); +} + +void mtk_pcie_save_timestamp(void) +{ + struct mono_time timestamp; + struct mtk_early_init *init = mtk_find_early_init(); + + if (!init) + return; + + timer_monotonic_get(&timestamp); + + init->pcie_timestamp_us = timestamp.microseconds; +} + +uint64_t mtk_pcie_perst_elapsed_time(void) +{ + struct mtk_early_init *init = mtk_find_early_init(); + struct mono_time cur_time; + + if (!init) + return 0; + + timer_monotonic_get(&cur_time); + + return cur_time.microseconds - init->pcie_timestamp_us; +} diff --git a/src/soc/mediatek/common/include/soc/early_init.h b/src/soc/mediatek/common/include/soc/early_init.h new file mode 100644 index 0000000..b8a08fa --- /dev/null +++ b/src/soc/mediatek/common/include/soc/early_init.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_EARLY_INIT_H +#define SOC_MEDIATEK_EARLY_INIT_H + +#include <soc/symbols.h> +#include <stdint.h> +#include <symbols.h> + +DECLARE_REGION(mtk_early_init); + +struct mtk_early_init { + long pcie_timestamp_us; +}; + +void mtk_clear_early_init(void); +void mtk_pcie_save_timestamp(void); +uint64_t mtk_pcie_perst_elapsed_time(void); + +#endif /* SOC_MEDIATEK_EARLY_INIT_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/63019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01f91b7fe2cbe4f73b5c616bb7aae778dee27d9a Gerrit-Change-Number: 63019 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8195: Add PCIe pre_init support in bootblock stage
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Hung-Te Lin. Jianjun Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63018 ) Change subject: soc/mediatek/mt8195: Add PCIe pre_init support in bootblock stage ...................................................................... soc/mediatek/mt8195: Add PCIe pre_init support in bootblock stage Add PCIe pre_init support in bootblock stage. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ic27f3ed7f1a6e3ff623d8754061547b55cd75d19 --- M src/soc/mediatek/mt8195/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63018/1 diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 68fe0f3..efb2c6f 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -8,6 +8,7 @@ bootblock-y += ../common/i2c.c i2c.c bootblock-y += ../common/mmu_operations.c bootblock-y += ../common/tracker.c ../common/tracker_v2.c +bootblock-$(CONFIG_PCI) += pcie.c bootblock-y += ../common/pll.c pll.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c timer.c -- To view, visit https://review.coreboot.org/c/coreboot/+/63018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic27f3ed7f1a6e3ff623d8754061547b55cd75d19 Gerrit-Change-Number: 63018 Gerrit-PatchSet: 1 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/pci: Add PCIe interfaces for MediaTek platform
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Jianjun Wang. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56794 to look at the new patch set (#23). Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform ...................................................................... libpayload/pci: Add PCIe interfaces for MediaTek platform Add PCIe configuration interfaces for MediaTek platform. The register base address of PCIe hardware might be different when it's a non-x86 platform, add 'pci_update_hw_base()' interface for users to update its base address to access PCIe hardware correctly. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/pcie_mediatek.c M payloads/libpayload/include/pci.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/56794/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/56794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea7d111fed6b816fa2352fe93c268116519a577 Gerrit-Change-Number: 56794 Gerrit-PatchSet: 23 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Hung-Te Lin <hungte(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-CC: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/pci: Split PCI interfaces as common and chip related
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Shelley Chen, Hung-Te Lin, Angel Pons, Yu-Ping Wu. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56789 to look at the new patch set (#22). Change subject: libpayload/pci: Split PCI interfaces as common and chip related ...................................................................... libpayload/pci: Split PCI interfaces as common and chip related Move the common APIs to pci_common.c and others to the chip related file. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 --- M payloads/libpayload/Kconfig M payloads/libpayload/drivers/Makefile.inc C payloads/libpayload/drivers/pci_io_ops.c A payloads/libpayload/drivers/pci_map_bus_ops.c R payloads/libpayload/drivers/pci_ops.c M payloads/libpayload/include/pci.h 6 files changed, 103 insertions(+), 102 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/56789/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/56789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74801bd4f3de51cbb574e86cd9bb09931152554 Gerrit-Change-Number: 56789 Gerrit-PatchSet: 22 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: Add timestamp to measure PERST# time
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Angel Pons, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Rex-BC Chen, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62933 to look at the new patch set (#2). Change subject: soc/mediatek: Add timestamp to measure PERST# time ...................................................................... soc/mediatek: Add timestamp to measure PERST# time Add timestamp support to measure the assertion time of PERST#. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the measured PERST# time: [DEBUG] mtk_pcie_domain_enable: 432517 us elapsed since assert PERST# [INFO ] mtk_pcie_domain_enable: PCIe link up success (17 tries) And the SSD information in boot log is as follows: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/pcie.c M src/soc/mediatek/mt8195/pcie.c 3 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/62933/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62933 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b7b6174abdf951af5796ab5ed141c45f32fc71 Gerrit-Change-Number: 62933 Gerrit-PatchSet: 2 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/cherry: Add PCIe domain support
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Hung-Te Lin, Shelley Chen, Paul Menzel, Angel Pons. Hello Hung-Te Lin, Shelley Chen, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62360 to look at the new patch set (#19). Change subject: mb/google/cherry: Add PCIe domain support ...................................................................... mb/google/cherry: Add PCIe domain support Add override device tree for dojo and add PCIe domain support. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 --- M src/mainboard/google/cherry/Kconfig A src/mainboard/google/cherry/variants/dojo/overridetree.cb 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/62360/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/62360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb02960504177fe488e6784b954c16b2c8d94972 Gerrit-Change-Number: 62360 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek: PCIe: Assert PERST# at bootblock stage
by Jianjun Wang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Shelley Chen, Rex-BC Chen, Angel Pons, Yu-Ping Wu, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Paul Menzel, Angel Pons, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62359 to look at the new patch set (#19). Change subject: soc/mediatek: PCIe: Assert PERST# at bootblock stage ...................................................................... soc/mediatek: PCIe: Assert PERST# at bootblock stage Described in PCIe CEM specification sections 2.2 (PERST# Signal) and 2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should be delayed 100ms (TPVPERL) for the power and clock to become stable. Instead of asserting PERST# right before PCIe initialization and wait for 100ms, assert the pin in bootblock stage so that the extra 100ms delay could be avoided. TEST=Build pass and boot up to kernel successfully via SSD on Dojo board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x15b7 PCI SSVID : 0x15b7 SN : 21517J440114 MN : WDC PC SN530 SDBPTPZ-256G-1006 RAB : 0x4 AERL : 0x7 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model WDC PC SN530 SDBPTPZ-256G-1006 BUG=b:178565024 BRANCH=cherry Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d --- M src/mainboard/google/cherry/bootblock.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/62359/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/62359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5b9369e6f8599f93415588ea585c952a41c5e7d Gerrit-Change-Number: 62359 Gerrit-PatchSet: 19 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: libpayload/vboot: Fix include paths fixup macro
by Jakub Czapiga (Code Review) 23 Mar '22

23 Mar '22

Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63002 ) Change subject: libpayload/vboot: Fix include paths fixup macro ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63002/comment/3c8448b8_17fc99f0 PS1, Line 11: ti > to Done File payloads/libpayload/vboot/Makefile.inc: https://review.coreboot.org/c/coreboot/+/63002/comment/e88f6265_23f52f30 PS1, Line 15: )% > Doesn't make much of a difference, but for consistency you should either have the slash here in both […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Gerrit-Change-Number: 63002 Gerrit-PatchSet: 1 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 09:14:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/vboot: Fix include paths fixup macro
by Jakub Czapiga (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jakub Czapiga. Hello build bot (Jenkins), Julius Werner, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63002 to look at the new patch set (#2). Change subject: libpayload/vboot: Fix include paths fixup macro ...................................................................... libpayload/vboot: Fix include paths fixup macro Include paths fixup macro for vboot was broken and was adding unnecessary prefix to paths from $(coreboottop). This patch adds correct filters to fix this behavior. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b --- M payloads/libpayload/vboot/Makefile.inc 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/63002/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Gerrit-Change-Number: 63002 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Updated Protectli fw6b documentations
by Felix Singer (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Xue Yao. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63016 ) Change subject: Documentation: Updated Protectli fw6b documentations ...................................................................... Patch Set 1: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63016/comment/ea0bb0cf_21e2906c PS1, Line 7: D docs/mb/protectli/fw6: Update documentation https://review.coreboot.org/c/coreboot/+/63016/comment/f40aa8a1_12b7866e PS1, Line 9: ME cleaner has been tested on the fw6b. More observations on the stock firmware has also been documented. Compatible boards are also listed along with the original manufacturer. Please wrap at 72 chars per line. File Documentation/mainboard/protectli/fw6.md: https://review.coreboot.org/c/coreboot/+/63016/comment/c0675606_7a71f63a PS1, Line 9: Remove leading spaces. There are more below. -- To view, visit https://review.coreboot.org/c/coreboot/+/63016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 1 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Xue Yao <xueyao(a)xyte.ch> Gerrit-Comment-Date: Wed, 23 Mar 2022 08:50:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2022