coreboot-gerrit March 2022

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Change in coreboot[master]: drivers/fsp1_1: Fix more strict-aliasing rules errors
by Patrick Rudolph (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Lee Leahy. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63017 ) Change subject: drivers/fsp1_1: Fix more strict-aliasing rules errors ...................................................................... drivers/fsp1_1: Fix more strict-aliasing rules errors Change-Id: If774ae6338dbb1ee2778d8c93cbb1868c61b1874 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_1/hob.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/63017/1 diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index 076dd5f..54056a8 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -26,20 +26,20 @@ /* Returns the next instance of a HOB type from the starting HOB. */ void *get_next_hob(uint16_t type, const void *hob_start) { - EFI_PEI_HOB_POINTERS hob; + EFI_HOB_GENERIC_HEADER *hdr; if (!hob_start) return NULL; - hob.Raw = (UINT8 *)hob_start; + hdr = (EFI_HOB_GENERIC_HEADER *)hob_start; /* Parse the HOB list until end of list or matching type is found. */ - while (!END_OF_HOB_LIST(hob.Raw)) { - if (hob.Header->HobType == type) - return hob.Raw; - if (GET_HOB_LENGTH(hob.Raw) < sizeof(*hob.Header)) + while (!END_OF_HOB_LIST(hdr)) { + if (hdr->HobType == type) + return (void *)hdr; + if (GET_HOB_LENGTH(hdr) < sizeof(*hdr)) break; - hob.Raw = GET_NEXT_HOB(hob.Raw); + hdr = GET_NEXT_HOB(hdr); } return NULL; } @@ -60,7 +60,7 @@ != NULL) { if (compare_guid(guid, &hob.Guid->Name)) break; - hob.Raw = GET_NEXT_HOB(hob.Raw); + hob.Raw = GET_NEXT_HOB(hob.Header); } return hob.Raw; } @@ -85,7 +85,7 @@ hob.Raw)) != NULL) { if (compare_guid(guid, &hob.ResourceDescriptor->Owner)) break; - hob.Raw = GET_NEXT_HOB(hob.Raw); + hob.Raw = GET_NEXT_HOB(hob.Header); } return hob.Raw; } -- To view, visit https://review.coreboot.org/c/coreboot/+/63017 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If774ae6338dbb1ee2778d8c93cbb1868c61b1874 Gerrit-Change-Number: 63017 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: TEST: Drop UEFI_2_4_BINDING
by Patrick Rudolph (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Lee Leahy. Hello Lee Leahy, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62993 to look at the new patch set (#3). Change subject: TEST: Drop UEFI_2_4_BINDING ...................................................................... TEST: Drop UEFI_2_4_BINDING See what breaks. Change-Id: Iedc4b082e850a31242208360a69b910d0df3191e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/drivers/intel/fsp1_1/Kconfig M src/drivers/intel/fsp1_1/hob.c 2 files changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/62993/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iedc4b082e850a31242208360a69b910d0df3191e Gerrit-Change-Number: 62993 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Documentation: Updated Protectli fw6b documentations
by Xue Yao (Code Review) 23 Mar '22

23 Mar '22

Xue Yao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63016 ) Change subject: Documentation: Updated Protectli fw6b documentations ...................................................................... Documentation: Updated Protectli fw6b documentations ME cleaner has been tested on the fw6b. More observations on the stock firmware has also been documented. Compatible boards are also listed along with the original manufacturer. Signed-off-by: Xue Yao <xueyao(a)xyte.ch> Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 --- M Documentation/mainboard/protectli/fw6.md 1 file changed, 22 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/63016/1 diff --git a/Documentation/mainboard/protectli/fw6.md b/Documentation/mainboard/protectli/fw6.md index 86449d1..76ada6d 100644 --- a/Documentation/mainboard/protectli/fw6.md +++ b/Documentation/mainboard/protectli/fw6.md @@ -4,6 +4,14 @@ ![](fw6.jpg) +## Stock firmware + +The stock firmware contains only the firmware descriptor, BIOS and +Management Engine. The EC firmware is not present on the SPI chip. + +Using ifdtool, a full layout can be obtained along with the ME and FD +flash regions. + ## Required proprietary blobs To build a minimal working coreboot image some blobs are required (assuming @@ -39,6 +47,9 @@ supporting the chipset is flashrom v1.1. Firmware an be easily flashed with internal programmer (either BIOS region or full image). +The stock firmware can be dumped using [flashrom] or downloaded from +Protectli's official website. + ### External programming The system has an internal flash chip which is a 8 MiB soldered SOIC-8 chip. @@ -67,7 +78,6 @@ the cables or not being populated on the board case. - Internal USB 2.0 headers -- Boot with cleaned ME ## Working @@ -83,7 +93,9 @@ - SeaBIOS payload (version rel-1.12.1) - Mini PCIe debug card connected to mSATA (mSATA slot has LPC signals routed) - Reset switch -- Booting Debian, Ubuntu, FreeBSD +- Booting Debian, Ubuntu, FreeBSD, Proxmox +- PCIe passthrough for NICs and iGPU +- Boot with cleaned ME ## Technology @@ -132,6 +144,14 @@ +------------------+--------------------------------------------------+ ``` +## Other compatible boards + +As Protectli licenses and uses [Yanling] appliances with no modifications +to the actual hardware, any compatible [Yanling] appliances would work. +Specifically, look for hardware with the same CPU and NIC and coreboot +should be able to compile and boot with no modifications required. + [Protectli FW6]: https://protectli.com/vault-6-port/ [MX25L6406E]: https://www.macronix.com/Lists/Datasheet/Attachments/7370/MX25L6406E,%203V,… [flashrom]: https://flashrom.org/Flashrom +[Yanling]: http://www.ylgkdn.cn/index.html -- To view, visit https://review.coreboot.org/c/coreboot/+/63016 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4938d81d57fc8172fefcc00222806fff0735d503 Gerrit-Change-Number: 63016 Gerrit-PatchSet: 1 Gerrit-Owner: Xue Yao <xueyao(a)xyte.ch> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Frank Wu (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak, Eric Lai, Amanda Hwang. Frank Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 07:28:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for...
by build bot (Jenkins) (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Kane Chen, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52244 ) Change subject: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for PCIe RPs ...................................................................... Patch Set 5: Verified+1 (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144515): https://review.coreboot.org/c/coreboot/+/52244/comment/5f0cdcd0_9a6087c6 PS5, Line 69: for (i = 0; i < cfg_count; i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/c/coreboot/+/52244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9 Gerrit-Change-Number: 52244 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 07:06:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for...
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Kane Chen, Patrick Rudolph. Hello build bot (Jenkins), Maulik V Vaghela, Rizwan Qureshi, Sugnan Prabhu S, Subrata Banik, Kane Chen, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/52244 to look at the new patch set (#4). Change subject: soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for PCIe RPs ...................................................................... soc/inte/alderlake: [TEST]Enable hotplug and configure free clock for PCIe RPs The patch enables hotplug, places PCIe in compliance test mode and Configures Clock sources to run free for EV test. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9 --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/52244/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/52244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5752bd1586e6062f740ca7a32df2135e26257b9 Gerrit-Change-Number: 52244 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [TEST]top/Makefile.inc: List the sub directory only for subdirs
by Bao Zheng (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63015 to review the following change. Change subject: [TEST]top/Makefile.inc: List the sub directory only for subdirs ...................................................................... [TEST]top/Makefile.inc: List the sub directory only for subdirs Change-Id: Ic59203d5c52fdce3a6a18ffb54f720f16804a85b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M Makefile.inc 1 file changed, 6 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/63015/1 diff --git a/Makefile.inc b/Makefile.inc index 929c236..a44aaef 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -79,12 +79,13 @@ ####################################################################### # root source directories of coreboot +subdirs-only=$(patsubst %/,%,$(filter-out $(wildcard $(patsubst %,%/,$(1))),$(sort $(dir $(wildcard $(1)/*/))))) subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common -subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*)) -subdirs-y += $(wildcard src/northbridge/*/*) -subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildcard src/superio/*/*) -subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) +subdirs-y += src/ec/acpi $(call subdirs-only,src/ec/*) $(call subdirs-only,src/southbridge/*) +subdirs-y += $(call subdirs-only,src/soc) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(call subdirs-only,src/soc/*)) +subdirs-y += $(call subdirs-only,src/northbridge/*) +subdirs-y += $(filter-out src/superio/common,$(call subdirs-only,src/superio)) $(call subdirs-only,src/superio/*) +subdirs-y += $(call subdirs-only,src/drivers) $(call subdirs-only,src/drivers/*) $(call subdirs-only,src/drivers/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu -- To view, visit https://review.coreboot.org/c/coreboot/+/63015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic59203d5c52fdce3a6a18ffb54f720f16804a85b Gerrit-Change-Number: 63015 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Amanda Hwang (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Frank Wu, Tim Wawrzynczak, Eric Lai. Amanda Hwang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... Patch Set 4: (1 comment) File src/mainboard/google/brya/variants/brya0/overridetree.cb: https://review.coreboot.org/c/coreboot/+/62998/comment/62084f91_c032da6f PS2, Line 617: register "hid" = ""MX98360A"" > tab Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 06:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter
by John Su (Code Review) 23 Mar '22

23 Mar '22

John Su has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62956 ) Change subject: mb/google/brya/var/felwinter: Update DPTF parameters for Felwinter ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/62956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30d1133cd1a145300b035efb790bca606f608e4e Gerrit-Change-Number: 62956 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: soc/intel/alderlake: Log CSE RO write protection info for ADL
by Sridhar Siricilla (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62987 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Log CSE RO write protection info for ADL ...................................................................... soc/intel/alderlake: Log CSE RO write protection info for ADL The patch logs write protection information for Alder Lake platform. As part of write protection information, coreboot logs status on CSE RO write protection and range. Also, triggers assert if EOM is disabled, and write protection for CSE RO is not enabled. TEST=Verify the write protection details on Gimble. Excerpt from Gimble coreboot log: [DEBUG] ME: WP for RO is enabled : YES [DEBUG] ME: RO write protection scope - Start=0x1000, End=0x15AFFF Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 --- M src/soc/intel/alderlake/me.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/62987/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766d5358bb7dd495b4a9b22a2f1b41dc90f3d8d5 Gerrit-Change-Number: 62987 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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