coreboot-gerrit March 2022

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Change in coreboot[master]: soc/intel/adl-n: Add device ID for TCSS XHCI
by Felix Held (Code Review) 23 Mar '22

23 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62955 ) Change subject: soc/intel/adl-n: Add device ID for TCSS XHCI ...................................................................... soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/usb4/xhci.c 2 files changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Krishna P Bhat D: Looks good to me, approved Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d1365f4..ff7d69a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4131,6 +4131,7 @@ #define PCI_DID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DID_INTEL_ADP_TCSS_XHCI 0x461e +#define PCI_DID_INTEL_ADP_N_TCSS_XHCI 0x464e #define PCI_DID_INTEL_ADP_M_XHCI 0x54ed #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 diff --git a/src/soc/intel/common/block/usb4/xhci.c b/src/soc/intel/common/block/usb4/xhci.c index 64e5601..20ed2a5 100644 --- a/src/soc/intel/common/block/usb4/xhci.c +++ b/src/soc/intel/common/block/usb4/xhci.c @@ -31,6 +31,7 @@ PCI_DID_INTEL_TGP_TCSS_XHCI, PCI_DID_INTEL_TGP_H_TCSS_XHCI, PCI_DID_INTEL_ADP_TCSS_XHCI, + PCI_DID_INTEL_ADP_N_TCSS_XHCI, 0 }; -- To view, visit https://review.coreboot.org/c/coreboot/+/62955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Gerrit-Change-Number: 62955 Gerrit-PatchSet: 6 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-CC: harsha.b.r(a)intel.com Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path
by Felix Held (Code Review) 23 Mar '22

23 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62493 ) Change subject: drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path ...................................................................... drivers/pc80/tpm/tis.c: Use fixed TPM ACPI path Windows 11 installer expects the TPM to reside under \\_SB_.PCI0 in ACPI device hierarchy, otherwise the TPM is not detected. Hardcode the path to fix the issue. TEST=Boot Windows 11 on Clevo NV41MZ and see the TPM is detected correctly TEST=Boot Ubuntu 20.04 on Clevo NV41MZ and see the TPM is detected correctly Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62493 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 2 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Michał Żygowski: Looks good to me, approved diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 455bcf9..cf46f76 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -779,12 +779,8 @@ #if CONFIG(HAVE_ACPI_TABLES) static void lpc_tpm_fill_ssdt(const struct device *dev) { - const char *path = acpi_device_path(dev->bus->dev); - - if (!path) { - path = "\\_SB_.PCI0.LPCB"; - printk(BIOS_DEBUG, "Using default TPM ACPI path: '%s'\n", path); - } + /* Windows 11 requires the following path for TPM to be detected */ + const char *path = "\\_SB_.PCI0"; /* Device */ acpigen_write_scope(path); -- To view, visit https://review.coreboot.org/c/coreboot/+/62493 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0b3136e3eb8eb1bb132132a5f3a7034bdd3b424 Gerrit-Change-Number: 62493 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/guybrush/var/nipperkin: update telemetry settings
by Karthik Ramasubramanian (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Kevin Chiu, Bhanu Prakash Maiya, Eric Peers, Rob Barnes. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62980 ) Change subject: mb/google/guybrush/var/nipperkin: update telemetry settings ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icad97644dd9391a325dfe1dbb1ec176e1f6d3dc3 Gerrit-Change-Number: 62980 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Eric Peers <epeers(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Attention: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Attention: Eric Peers <epeers(a)google.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 14:53:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62949 ) Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold ...................................................................... mb/google/brya/var/primus{4es}: add delay time to rtd3-cold This CL adds the delay time into the RTD3 sequence, which will turn off the eMMC controller (a true D3cold state) during the RTD3 sequence.We checked power on sequence requires enable pin prior to reset pin, added delay to meet the sequence and test passed on various eMMC SKUs.Base on BH799BB_Preliminary_DS_R079_20201124.pdf in chapter 7.2. BUG=b:224648680 TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage test suspend stress 2500 cycles passed on primus Signed-off-by: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62949 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/variants/primus/overridetree.cb M src/mainboard/google/brya/variants/primus4es/overridetree.cb 2 files changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/primus/overridetree.cb b/src/mainboard/google/brya/variants/primus/overridetree.cb index 8832381..c01516c 100644 --- a/src/mainboard/google/brya/variants/primus/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus/overridetree.cb @@ -147,6 +147,8 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 diff --git a/src/mainboard/google/brya/variants/primus4es/overridetree.cb b/src/mainboard/google/brya/variants/primus4es/overridetree.cb index 940c63f..e2b8d02 100644 --- a/src/mainboard/google/brya/variants/primus4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/primus4es/overridetree.cb @@ -141,6 +141,8 @@ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E20)" register "srcclk_pin" = "6" + register "reset_delay_ms" = "50" + register "enable_delay_ms" = "20" device generic 0 alias emmc_rtd3 on end end # Enable PCIe-to-eMMC bridge PCIE 3 using clk 6 -- To view, visit https://review.coreboot.org/c/coreboot/+/62949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Gerrit-Change-Number: 62949 Gerrit-PatchSet: 8 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Terry Chen, Paul Menzel. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62949 ) Change subject: mb/google/brya/var/primus{4es}: add delay time to rtd3-cold ...................................................................... Patch Set 7: Code-Review+2 (1 comment) Patchset: PS3: > Hi Tim, we already update the test result in b:224648680, please help to review. Thanks. Thanks Terry! -- To view, visit https://review.coreboot.org/c/coreboot/+/62949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ab4fdf0ee73b819b3c203e995ac9d5ae0d24bd0 Gerrit-Change-Number: 62949 Gerrit-PatchSet: 7 Gerrit-Owner: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.com> Gerrit-CC: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-CC: Zoey Wu <zoey_wu(a)wistron.corp-partner.google.com> Gerrit-Attention: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 14:37:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add workaround for Ti50
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak, Christian Walter. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63011 ) Change subject: drivers/i2c/tpm: Add workaround for Ti50 ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63011/comment/dc63330c_cabb7e90 PS3, Line 10: workaroud > `workaround` Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 14:10:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add workaround for Ti50
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Christian Walter, Eric Lai. Hello build bot (Jenkins), Kangheui Won, Reka Norman, Tim Wawrzynczak, Christian Walter, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63011 to look at the new patch set (#4). Change subject: drivers/i2c/tpm: Add workaround for Ti50 ...................................................................... drivers/i2c/tpm: Add workaround for Ti50 Ti50 FW under 0.15 is not support board cfg. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d --- M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/cr50.c M src/mainboard/google/brya/Kconfig 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63011/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 4 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/i2c/tpm: Add workaround for Ti50
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Christian Walter, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63011 ) Change subject: drivers/i2c/tpm: Add workaround for Ti50 ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63011/comment/9fc19a85_65fe9f0e PS3, Line 10: workaroud `workaround` -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 3 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 14:09:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/usb/ehci_debug.c: Fix building with clang
by Kyösti Mälkki (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61891 ) Change subject: drivers/usb/ehci_debug.c: Fix building with clang ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61891 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf5fd69fbf54b0d40bfdb17d1396d77dcb0a6060 Gerrit-Change-Number: 61891 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 23 Mar 2022 14:03:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 23 Mar '22

23 Mar '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63025 ) Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already setup in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/cpu.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63025/1 diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index adc99d0..13db61f 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -11,6 +11,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -37,7 +38,8 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + if (!acpi_is_wakeup_s3()) // SMMINFO was already setup in S5 + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit March 2022