coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init
by Raul Rangel (Code Review) 23 Mar '22

23 Mar '22

Raul Rangel has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62880 ) Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init ...................................................................... soc/amd/common/psp_verstage: Write postcodes after ESPI init On boards where PSP uses ESPI to write postcodes, update the verstage to do it after ESPI initialization. BUG=b:224543620 TEST=Build and boot to OS in Nipperkin. Ensure that there are no attempts to write the post code from PSP verstage before ESPI initialization. Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62880 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Mohan Viswanathan Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/common/psp_verstage/psp_verstage.c 2 files changed, 16 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Mohan Viswanathan: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 81cf974..48944c8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -345,6 +345,14 @@ help Disables the output of port80 post codes from PSP. +config PSP_POSTCODES_ON_ESPI + bool "Use eSPI bus for PSP post codes" + depends on !PSP_DISABLE_POSTCODES + default y + help + Select to send PSP port80 post codes on eSPI bus. + If not selected, PSP port80 codes will be sent on LPC bus. + config PSP_INIT_ESPI bool "Initialize eSPI in PSP Stage 2 Boot Loader" help diff --git a/src/soc/amd/common/psp_verstage/psp_verstage.c b/src/soc/amd/common/psp_verstage/psp_verstage.c index 9d0fb22..d64c257 100644 --- a/src/soc/amd/common/psp_verstage/psp_verstage.c +++ b/src/soc/amd/common/psp_verstage/psp_verstage.c @@ -206,16 +206,21 @@ /* * Do not use printk() before console_init() * Do not use post_code() before verstage_mainboard_init() + * Do not use svc_write_postcode before verstage_soc_espi_init() if PSP uses ESPI + * to write postcodes. */ timestamp_init(timestamp_get()); - svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_ENTERED_PSP_VERSTAGE); svc_debug_print("Entering verstage on PSP\n"); memset(&_bss_start, '\0', &_bss_end - &_bss_start); - svc_write_postcode(POSTCODE_CONSOLE_INIT); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_CONSOLE_INIT); console_init(); - svc_write_postcode(POSTCODE_EARLY_INIT); + if (!CONFIG(PSP_POSTCODES_ON_ESPI)) + svc_write_postcode(POSTCODE_EARLY_INIT); retval = verstage_soc_early_init(); if (retval) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/62880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Gerrit-Change-Number: 62880 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/amd/common/psp_verstage: Write postcodes after ESPI init
by Raul Rangel (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Jon Murphy, Avinash Alevoor, Rob Barnes, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62880 ) Change subject: soc/amd/common/psp_verstage: Write postcodes after ESPI init ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b78931c741c75dc845c9b34e3b2b896221f2364 Gerrit-Change-Number: 62880 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Avinash Alevoor Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 16:13:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: driver/wifi: Add _DSM method for DDRRFIM
by Varshit B Pandya (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Varshit B Pandya, Subrata Banik, Maulik V Vaghela, Paul Menzel, Sugnan Prabhu S, Tim Wawrzynczak. Hello build bot (Jenkins), Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Rizwan Qureshi, Sugnan Prabhu S, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61020 to look at the new patch set (#24). Change subject: driver/wifi: Add _DSM method for DDRRFIM ...................................................................... driver/wifi: Add _DSM method for DDRRFIM coreboot needs to propagate the CnviDdrRfim value info of the feature enable/disable state into the CNVi via the WiFi DSM ACPI object. This will be consumed by the Wi-Fi driver and it will act according to CB enablement configuration. This patch adds _DSM method for that. Add support for following 2 functions in _DSM method - Function 0: Function Support Query Returns a bitmask of functions supported. - Function 3: RFI enablement 0 Feature Enable 1 Feature Disable BUG=b:201724512 TEST=Build, boot brya0 and dump SSDT entries Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { ToBuffer (Arg0, Local0) If ((Local0 == ToUUID ("7266172c-220b-4b29-814f-75e4dd26b5fd"))) { ToInteger (Arg2, Local1) If ((Local1 == Zero)) { Return (Buffer (One) { 0x09 }) } If ((Local1 == One)){} If ((Local1 == 0x02)){} If ((Local1 == 0x03)) { Return (Zero) } Return (Buffer (One) { 0x00 }) } Return (Buffer (One) { 0x00 }) } Signed-off-by: Varshit B Pandya <varshit.b.pandya(a)intel.com> Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 --- M src/drivers/wifi/generic/acpi.c 1 file changed, 66 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61020/24 -- To view, visit https://review.coreboot.org/c/coreboot/+/61020 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I217b736df3d4224a6732d1941a160abcddbd8f37 Gerrit-Change-Number: 61020 Gerrit-PatchSet: 24 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/alderlake: Send EOP over multithreaded environment
by build bot (Jenkins) (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63028 ) Change subject: soc/intel/alderlake: Send EOP over multithreaded environment ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/chip.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144567): https://review.coreboot.org/c/coreboot/+/63028/comment/a95ab9b6_5c0248a0 PS1, Line 172: mp_run_on_aps(&send_eop_on_non_bsp, NULL, boot_cpu() + 1, 1000 * USECS_PER_MSEC); line over 96 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/63028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe4a56d7f52b0cd7133acd8c434cd3ee1bd9297 Gerrit-Change-Number: 63028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 16:04:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Send EOP over multithreaded environment
by Subrata Banik (Code Review) 23 Mar '22

23 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63028 ) Change subject: soc/intel/alderlake: Send EOP over multithreaded environment ...................................................................... soc/intel/alderlake: Send EOP over multithreaded environment This patch sends CSE EOP command using non-BSP core. TEST=Able to see CSE EOP command is successful. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Iabe4a56d7f52b0cd7133acd8c434cd3ee1bd9297 --- M src/soc/intel/alderlake/chip.c 1 file changed, 9 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/63028/1 diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 699b39d..91ce8a3 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <device/pci.h> +#include <cpu/x86/mp.h> #include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/acpi.h> @@ -18,6 +19,8 @@ #include <soc/pcie.h> #include <soc/ramstage.h> #include <soc/soc_chip.h> +#include <smp/node.h> +#include <timer.h> #if CONFIG(HAVE_ACPI_TABLES) const char *soc_acpi_name(const struct device *dev) @@ -134,6 +137,11 @@ gpio_pm_configure(value, TOTAL_GPIO_COMM); } +static void send_eop_on_non_bsp(void *unused) +{ + cse_send_end_of_post(); +} + void soc_init_pre_device(void *chip_info) { /* Perform silicon specific init. */ @@ -161,7 +169,7 @@ */ if (CONFIG(SOC_INTEL_CSE_SEND_EOP_EARLY)) { printk(BIOS_INFO, "Sending EOP early from SoC\n"); - cse_send_end_of_post(); + mp_run_on_aps(&send_eop_on_non_bsp, NULL, boot_cpu() + 1, 1000 * USECS_PER_MSEC); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/63028 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iabe4a56d7f52b0cd7133acd8c434cd3ee1bd9297 Gerrit-Change-Number: 63028 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62986 ) Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/spi/spi.c: https://review.coreboot.org/c/coreboot/+/62986/comment/0cd4481f_fcb8ec13 PS3, Line 53: #if ENV_RAMSTAGE > This is not required. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 15:50:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
by Subrata Banik (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans, Eric Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63009 ) Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/63009/comment/6a06176d_637b82f4 PS2, Line 43: select FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT > > Can we depend CONFIG_CONSOLE_SERIAL or CONFIG_UART_DEBUG? I think the normal image, we don't need to know FSP log. > > Isn't the whole point to be console agnostic and let coreboot do the console printing wherever it seems fit? Even without series I still see value in printing output to for instance the cbmem console. Unless u have debug FSP image in repository, you won't see the FSP debug log with normal image. But I understood your point, and that can only happen when we have unified FSP binary which is debug always then, it's all about coreboot, how coreboot decides to control the serial log enable/disable. i'm working on a further change list to keep a reduced debug binary so we don't need to have separate FSP build flag while debugging any issue, rather can use coreboot to enable the FSP debug in verbose mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/63009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a0530a282657e379a00c3e7d0ed8148dd5e9196 Gerrit-Change-Number: 63009 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 15:40:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63008 ) Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Gerrit-Change-Number: 63008 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 15:36:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Andrey Petrov. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63007 ) Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler ...................................................................... Patch Set 2: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63007/comment/6a5c8249_d6b99aa7 PS2, Line 29: serialport nit: `serial port` File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/63007/comment/0ccb1b20_cc41580e PS2, Line 355: _IN_COREBOOT nit: this part of the name seems redundant 😊 -- To view, visit https://review.coreboot.org/c/coreboot/+/63007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 Gerrit-Change-Number: 63007 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 15:35:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: include/efi: Add EFI Status code definitions
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63006 ) Change subject: include/efi: Add EFI Status code definitions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Gerrit-Change-Number: 63006 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 15:31:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022