coreboot-gerrit March 2022

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Change in coreboot[master]: checkpatch.conf: Disable gerrit change ID for coreboot
by Felix Singer (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Martin Roth, Paul Menzel. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63030 ) Change subject: checkpatch.conf: Disable gerrit change ID for coreboot ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6efb5559027ed9497ee85497bb4b4e786f9901 Gerrit-Change-Number: 63030 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 18:23:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: util/lint/checkpatch: Update commit message & subject line limits
by Felix Singer (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Martin Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63029 ) Change subject: util/lint/checkpatch: Update commit message & subject line limits ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712 Gerrit-Change-Number: 63029 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 18:22:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: checkpatch.conf: Disable gerrit change ID for coreboot
by Elyes Haouas (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Martin Roth, Paul Menzel. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63030 ) Change subject: checkpatch.conf: Disable gerrit change ID for coreboot ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/63030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f6efb5559027ed9497ee85497bb4b4e786f9901 Gerrit-Change-Number: 63030 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 23 Mar 2022 18:15:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs
by Michał Żygowski (Code Review) 23 Mar '22

23 Mar '22

Michał Żygowski has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62210 ) Change subject: mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs ...................................................................... mb/dell/optiplex_9010/sch5545_ec.c: Fix HWM initialization bugs Fix the HWM sequence matching to the chassis. HWM sequence for SFF was incorrectly passed to MT chassis HWM initialization. Vendor code also applies a fix-up for MT/DT chassis. This fixup was missing one register read compared to the vendor code. Add the missing read and guard the fixup depening on the returned value to match the vendor code behavior. Not doing so resulted in increased fan speeds on Dell Precision T1650 compared to Dell's firmware. TEST=Boot Dell Precision T1650 and hear the fans are as silent as on Dell's firmware Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62210 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/mainboard/dell/optiplex_9010/sch5545_ec.c 1 file changed, 24 insertions(+), 20 deletions(-) Approvals: build bot (Jenkins): Verified Krystian Hebel: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9010/sch5545_ec.c b/src/mainboard/dell/optiplex_9010/sch5545_ec.c index fa78a98..9aa0038 100644 --- a/src/mainboard/dell/optiplex_9010/sch5545_ec.c +++ b/src/mainboard/dell/optiplex_9010/sch5545_ec.c @@ -548,17 +548,17 @@ switch (chassis_id) { case 0x0: case 0x4: - return 5; + return 5; /* MT */ case 0x8: - return 4; + return 4; /* DT */ case 0x3: case 0xb: - return 3; + return 3; /* USFF */ case 0x1: case 0x9: case 0x5: case 0xd: - return 6; + return 6; /* SFF */ default: printk(BIOS_DEBUG, "Unknown chassis ID %x\n", chassis_id); break; @@ -640,7 +640,7 @@ ec_hwm_init_late(ec_hwm_chassis4, ARRAY_SIZE(ec_hwm_chassis4)); break; case 5: - ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis5)); + ec_hwm_init_late(ec_hwm_chassis5, ARRAY_SIZE(ec_hwm_chassis5)); break; case 6: ec_hwm_init_late(ec_hwm_chassis6, ARRAY_SIZE(ec_hwm_chassis6)); @@ -673,21 +673,25 @@ ec_read_write_reg(EC_HWM_LDN, 0x00b8, &val, READ_OP); if (chassis_type == 4 || chassis_type == 5) { - ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP); - val &= 0xfb; - ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP); - ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP); - val &= 0xfb; - ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP); - ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP); - val &= 0xfb; - ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP); - val = 0x99; - ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP); - val = 0x47; - ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP); - val = 0x91; - ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x0027, &val, READ_OP); + if (val == 0) { + printk(BIOS_INFO, "Applying HWM fix-up for MT/DT chassis\n"); + ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a0, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a1, &val, WRITE_OP); + ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, READ_OP); + val &= 0xfb; + ec_read_write_reg(EC_HWM_LDN, 0x00a2, &val, WRITE_OP); + val = 0x99; + ec_read_write_reg(EC_HWM_LDN, 0x008a, &val, WRITE_OP); + val = 0x47; + ec_read_write_reg(EC_HWM_LDN, 0x008b, &val, WRITE_OP); + val = 0x91; + ec_read_write_reg(EC_HWM_LDN, 0x008c, &val, WRITE_OP); + } } ec_read_write_reg(EC_HWM_LDN, 0x0049, &val, READ_OP); 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/62210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c0e1c00e69d66848a602ad91a3e83375a095f44 Gerrit-Change-Number: 62210 Gerrit-PatchSet: 4 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: util/lint/checkpatch: Update commit message & subject line limits
by Elyes Haouas (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Martin Roth. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63029 ) Change subject: util/lint/checkpatch: Update commit message & subject line limits ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712 Gerrit-Change-Number: 63029 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 18:13:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Make coreboot ARM BBR compliant
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63034 to review the following change. Change subject: Docs/project_ideas: Make coreboot ARM BBR compliant ...................................................................... Docs/project_ideas: Make coreboot ARM BBR compliant Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/contributing/project_ideas.md 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/63034/1 diff --git a/Documentation/contributing/project_ideas.md b/Documentation/contributing/project_ideas.md index 75c78ca..5d7b4496 100644 --- a/Documentation/contributing/project_ideas.md +++ b/Documentation/contributing/project_ideas.md @@ -228,3 +228,34 @@ ### Mentors * Patrick Rudolph <patrick.rudolph(a)9elements.com> * Christian Walter <christian.walter(a)9elements.com> + +## Make coreboot ARM (L)BBR compliant +The ARM [BBR](https://developer.arm.com/documentation/den0044/f/), Base Boot +Requirements is a firmware specification describing how ARM64 servers and +hyperscalers should load an operating system. The main purpose of this +specification is to boot Operating systems like Linux without +[devicetree](https://www.kernel.org/doc/html/latest/devicetree/usage-model.html) +but using SMBIOS, ACPI and UEFI runtime services. + +Currently coreboot has no support for SMBIOS or ACPI. +coreboot also does not support runtime services by design. +The mandated UEFI runtime services seem only useful to provide Linux both +SMBIOS & ACPI. + +So the scope of this project would be: +* Port the QEMU aarch64 sbsa-ref machine to coreboot +* Implement SMBIOS on ARM64 +* Implement ACPI on ARM64 +* Investigate how to provide minimal UEFI runtime services, e.g. in a payload + or better find an (upstreamable) way in Linux on how to pass ACPI & SMBIOS without + UEFI runtime services + +### Requirements +* Hardware knowledge: Nothing (target is emulated) +* coreboot knowledge: Know how tables are generated/injected and passed to + Payloads +* Linux knowledge: Being able to compile and debug it. Some knowledge on the + boot process is certainly helpful. + +### Mentors +* Arthur Heymans <arthur.heymans(a)9elements.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63025 ) Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/63025/comment/6a68b255_1abcc5ce PS1, Line 9: setup > The verb is spelled with a space: set up. Done File src/soc/amd/cezanne/cpu.c: https://review.coreboot.org/c/coreboot/+/63025/comment/29364fb9_637a143e PS1, Line 41: setup > set up Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 18:02:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63025 to look at the new patch set (#2). Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/cpu.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63025/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size
by Karthik Ramasubramanian (Code Review) 23 Mar '22

23 Mar '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63033 ) Change subject: mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size ...................................................................... mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size ABL generates memory training data whose size is ~80KiB. So increase the RW_MRC_CACHE region size to accommodate that. BUG=b:224618411 TEST=Build and boot to payload in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 --- M src/mainboard/google/skyrim/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/63033/1 diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd index a6dbc2c..c114c03 100644 --- a/src/mainboard/google/skyrim/chromeos.fmd +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE(PRESERVE) 64K + RW_MRC_CACHE(PRESERVE) 96K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/63033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 Gerrit-Change-Number: 63033 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Tim Wawrzynczak (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Subrata Banik, Sridhar Siricilla. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62986 ) Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 4 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 17:22:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022