coreboot-gerrit March 2022

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Change in coreboot[master]: amd/fam15tn/gcccar.inc: Fix msr access with clang
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63044 to review the following change. Change subject: amd/fam15tn/gcccar.inc: Fix msr access with clang ...................................................................... amd/fam15tn/gcccar.inc: Fix msr access with clang Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/amd/agesa/f15tn/gcccar.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/63044/1 diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 5a0c1c4..fb49c17 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -971,9 +971,9 @@ 1: #.if (al == 01h) # TN only #Enable MSRC001_001F[EnableCf8ExtCfg] mov $NB_CFG, %ecx # MSR:C001_001F - _rdmsr + _RDMSR bts $(ENABLE_CF8_EXT_CFG - 32), %edx - _wrmsr + _WRMSR # Set F3x44[6, CpuErrDis] = 1 MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG //mov $(1 << 31 | 2 << 28 | (((MCA_NB_CFG) & (0x0F00)) >> 8) << 24 | 2 << 16 | 1 << 11 | FUNC_3 << 8), %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/63044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21bebd475dce373a77626d2e78a0ab10678ea8b6 Gerrit-Change-Number: 63044 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/f15tn/gcccar.inc: Fix macro with Clang
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63043 to review the following change. Change subject: amd/f15tn/gcccar.inc: Fix macro with Clang ...................................................................... amd/f15tn/gcccar.inc: Fix macro with Clang Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/amd/agesa/f15tn/gcccar.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/63043/1 diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index 68eaed8..5a0c1c4 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -224,7 +224,7 @@ .endm .macro MAKE_EXT_PCI_ADDR Seg, Bus, Dev, Func, Offset - mov $(1 << 31 | (Seg) << 28 | (((Offset) & (0x0F00)) >> 8) << 24 | (Bus) << 16 | (Dev) << 11 | (Func) << 8) | ((Offset) & (0xFC)), %eax + mov $(1 << 31 | (\Seg) << 28 | (((\Offset) & (0x0F00)) >> 8) << 24 | (\Bus) << 16 | (\Dev) << 11 | (\Func) << 8) | ((\Offset) & (0xFC)), %eax .endm /**************************************************************************** * -- To view, visit https://review.coreboot.org/c/coreboot/+/63043 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d95ac9d548e410a81188307cc92f77224baea0e Gerrit-Change-Number: 63043 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/fam*/northbridge.c: Remove unused reset_memhole variable
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63042 to review the following change. Change subject: amd/fam*/northbridge.c: Remove unused reset_memhole variable ...................................................................... amd/fam*/northbridge.c: Remove unused reset_memhole variable Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 3 files changed, 3 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/63042/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 77e68d8..3507ff7 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -510,7 +510,6 @@ struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -539,10 +538,8 @@ mem_hole = get_hw_mem_hole_info(); // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } #endif idx = 0x10; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 65be7d8..d36c9d4 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -668,7 +668,6 @@ struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -697,10 +696,8 @@ mem_hole = get_hw_mem_hole_info(); // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } #endif idx = 0x10; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 1c63092..170a0d2 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -680,7 +680,6 @@ struct bus *link; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info mem_hole; - u32 reset_memhole = 1; #endif pci_tolm = 0xffffffffUL; @@ -709,10 +708,8 @@ mem_hole = get_hw_mem_hole_info(); // Use hole_basek as mmio_basek, and we don't need to reset hole anymore - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { + if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) mmio_basek = mem_hole.hole_startk; - reset_memhole = 0; - } #endif idx = 0x10; -- To view, visit https://review.coreboot.org/c/coreboot/+/63042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb Gerrit-Change-Number: 63042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/fam*/northbridge.c: Fix unused hest variable
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63041 to review the following change. Change subject: amd/fam*/northbridge.c: Fix unused hest variable ...................................................................... amd/fam*/northbridge.c: Fix unused hest variable The variable actually makes to code look a lot better. TESTED: BUILD_TIMELESS=1 results in identical binaries Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c 3 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/63041/1 diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 5a8b24d..77e68d8 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -714,9 +714,9 @@ /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; /* SRAT */ current = ALIGN(current, 8); diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 6994781..65be7d8 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -475,9 +475,9 @@ /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 865f5cf..1c63092 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -469,9 +469,9 @@ /* HEST */ current = ALIGN(current, 8); hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; + acpi_write_hest(hest, acpi_fill_hest); + acpi_add_table(rsdp, hest); + current += hest->header.length; current = ALIGN(current, 8); printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); -- To view, visit https://review.coreboot.org/c/coreboot/+/63041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800 Gerrit-Change-Number: 63041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/amd/agesa: Add CFLAGS required by CLANG
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63040 to review the following change. Change subject: vendorcode/amd/agesa: Add CFLAGS required by CLANG ...................................................................... vendorcode/amd/agesa: Add CFLAGS required by CLANG Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/vendorcode/amd/agesa/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/63040/1 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..73a87a3 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -11,6 +11,11 @@ libagesa-generic-ccopts += -D__LIBAGESA__ libagesa-generic-ccopts += -fno-zero-initialized-in-bss libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +libagesa-generic-ccopts += -Wno-pragma-pack -Wno-unused-but-set-variable +libagesa-generic-ccopts += -Wno-implicit-fallthrough + +romstage-generic-ccopts += -Wno-pragma-pack +ramstage-generic-ccopts += -Wno-pragma-pack AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing -- To view, visit https://review.coreboot.org/c/coreboot/+/63040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Gerrit-Change-Number: 63040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Raul Rangel (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63025 ) Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/cezanne/cpu.c: https://review.coreboot.org/c/coreboot/+/63025/comment/cd8b75e4_8786f177 PS2, Line 41: was already set up This is a bit confusing. Set up by who? How about: SMMINFO only needs to be setup when booting from S5. -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 20:57:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Docs/project_ideas: Make coreboot ARM BBR compliant
by Julius Werner (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans, Felix Singer, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 ) Change subject: Docs/project_ideas: Make coreboot ARM BBR compliant ...................................................................... Patch Set 1: (1 comment) File Documentation/contributing/project_ideas.md: https://review.coreboot.org/c/coreboot/+/63034/comment/3ed8c37c_a8117809 PS1, Line 232: ## Make coreboot ARM (L)BBR compliant It would be nice if this could emphasize a bit more that this is an _optional_ alternative configuration, and it should be implemented in a way that in no way compromises the existing use cases (not even with extra bloat). "Make coreboot compliant" just sounds like there's a bug with the existing coreboot support that needs to be fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/63034 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f5f1f0a613ed0ed3f8ecdf3c1330a0d78efe399 Gerrit-Change-Number: 63034 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 20:49:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Fix Backlight GPIO
by 9elements QA (Code Review) 23 Mar '22

23 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63003 ) Change subject: mb/google/skyrim: Fix Backlight GPIO ...................................................................... Patch Set 3: Automatic boot test returned (PASS/FAIL/TOTAL): 10 / 1 / 11 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96762 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96761 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/96760 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/96759 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/96758 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96757 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/96756 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/96755 FAIL: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96754 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/96752 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX and payload SeaBIOS : https://lava.9esec.io/r/96751 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ife3335ca5a3c2517a6817fccf0544e5fcacb1f9d Gerrit-Change-Number: 63003 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 20:48:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/*: Fix CPPFLAGS
by Arthur Heymans (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63039 to review the following change. Change subject: drivers/*: Fix CPPFLAGS ...................................................................... drivers/*: Fix CPPFLAGS These are CPPFLAGS not CFLAGS. Change-Id: I10d693215ce72a9c5fc76df56f9284dedbe4c41e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/i2c/pca9538/Makefile.inc M src/drivers/intel/i210/Makefile.inc 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/63039/1 diff --git a/src/drivers/i2c/pca9538/Makefile.inc b/src/drivers/i2c/pca9538/Makefile.inc index 8b7fa25..92c4cfb 100644 --- a/src/drivers/i2c/pca9538/Makefile.inc +++ b/src/drivers/i2c/pca9538/Makefile.inc @@ -1,5 +1,5 @@ ramstage-$(CONFIG_DRIVERS_I2C_PCA9538) += pca9538.c ifeq ($(CONFIG_DRIVERS_I2C_PCA9538),y) -CFLAGS_common += -Isrc/drivers/i2c/pca9538 +CPPFLAGS_common += -Isrc/drivers/i2c/pca9538 endif diff --git a/src/drivers/intel/i210/Makefile.inc b/src/drivers/intel/i210/Makefile.inc index 218b1b4..d3e006e 100644 --- a/src/drivers/intel/i210/Makefile.inc +++ b/src/drivers/intel/i210/Makefile.inc @@ -3,5 +3,5 @@ ramstage-$(CONFIG_DRIVER_INTEL_I210)+= i210.c ifeq ($(CONFIG_DRIVER_INTEL_I210),y) -CFLAGS_x86_32 += -Isrc/drivers/intel/i210 +CPPFLAGS_common += -Isrc/drivers/intel/i210 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/63039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10d693215ce72a9c5fc76df56f9284dedbe4c41e Gerrit-Change-Number: 63039 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: amdfwtool: Change the some FW's level for A/B recovery
by Felix Held (Code Review) 23 Mar '22

23 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62329 ) Change subject: amdfwtool: Change the some FW's level for A/B recovery ...................................................................... amdfwtool: Change the some FW's level for A/B recovery The Pubkey(0), PSP bootloader(1) and IKEK(0x21) should be put to level 2 only for A/B recovery for Sabrina, which is going to be the long term and A/B recovery layout only. So the amdfwtool should be changed for Sabrina. The old levels of these 3 FWs are for Cezanne, which doesn't use AB recovery now. Just set the specific field levels in generic Cezanne folder for demo. Leave the fw.cfg in Guybrush unchanged. Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62329 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Jason Glenesk <jason.glenesk(a)gmail.com> --- M src/soc/amd/cezanne/fw.cfg M util/amdfwtool/amdfwtool.c 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jason Glenesk: Looks good to me, but someone else must approve diff --git a/src/soc/amd/cezanne/fw.cfg b/src/soc/amd/cezanne/fw.cfg index 565ab7a..b733c45 100644 --- a/src/soc/amd/cezanne/fw.cfg +++ b/src/soc/amd/cezanne/fw.cfg @@ -4,9 +4,9 @@ # type file # PSP -AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn +AMD_PUBKEY_FILE TypeId0x00_CezannePublicKey.tkn Lxb PSPBTLDR_FILE TypeId0x01_PspBootLoader_CZN.sbin -PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin +PSPBTLDR_AB_STAGE1_FILE TypeId0x01_PspBootLoader_AB_Stage1_CZN.sbin Lx1 PSPBTLDR_WL_FILE TypeId0x01_PspBootLoader_WL_CZN.sbin PSPSECUREOS_FILE TypeId0x02_PspOS_CZN.sbin PSPRCVR_FILE TypeId0x03_PspRecoveryBootLoader_CZN.sbin @@ -16,7 +16,7 @@ PSP_SMUFW2_SUB0_FILE TypeId0x12_SmuFirmware2_CZN.csbin PSP_SEC_DEBUG_FILE TypeId0x13_PspEarlyUnlock_CZN.sbin PSP_HW_IPCFG_FILE TypeId0x20_HwIpCfg_CZN_A0.sbin -PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin +PSP_IKEK_FILE TypeId0x21_PspIkek_CZN.bin Lxb PSP_SECG0_FILE TypeId0x24_SecurePolicyL0_CZN.sbin PSP_MP2FW0_FILE TypeId0x25_Mp2Fw_CZN.sbin AMD_DRIVER_ENTRIES TypeId0x28_PspSystemDriver_CZN.sbin diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index f5b73d2..8023595 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -221,8 +221,8 @@ } amd_fw_entry amd_psp_fw_table[] = { - { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL1_AB }, + { .type = AMD_FW_PSP_PUBKEY, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_PSP_BOOTLOADER, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_RECOVERY, .level = PSP_LVL1 }, { .type = AMD_FW_PSP_RTM_PUBKEY, .level = PSP_BOTH }, @@ -240,7 +240,7 @@ { .type = AMD_PSP_FUSE_CHAIN, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_TOKEN_UNLOCK, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_SEC_GASKET, .subprog = 0, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_SEC_GASKET, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, -- To view, visit https://review.coreboot.org/c/coreboot/+/62329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11092b52927b2c526a5be719104ba39a790b6fa8 Gerrit-Change-Number: 62329 Gerrit-PatchSet: 21 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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