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Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63025 )
Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/cezanne/cpu.c:
https://review.coreboot.org/c/coreboot/+/63025/comment/5752465f_f2107f29
PS2, Line 41: was already set up
> This is a bit confusing. Set up by who? […]
Done
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63049 )
Change subject: soc/amd/sabrina: update soft fuse bit 15 definition
......................................................................
soc/amd/sabrina: update soft fuse bit 15 definition
For SoC that don't support LPC any more the definition of the PSP soft
fuse chain bit 15 has changed. Earlier SoCs that still supported a
physical LPC bus used this bit to determine if the I/O port 0x80 POST
code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a
physical LPC bus any more and on those this bit selects if the PSP debug
output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that
the needs to be decoded to eSPI.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232
---
M src/soc/amd/sabrina/Kconfig
M src/soc/amd/sabrina/Makefile.inc
2 files changed, 2 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/63049/1
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 1be53b5..b8cf728 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -397,8 +397,8 @@
Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG)
Bit 7: Disable PSP postcodes on Renoir and newer chips only
(Set by PSP_DISABLE_PORT80)
- Bit 15: PSP post code destination: 0=LPC 1=eSPI
- (Set by PSP_INITIALIZE_ESPI)
+ Bit 15: PSP debug output destination:
+ 0=SoC MMIO UART, 1=IO port 0x3F8
Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW)
See #55758 (NDA) for additional bit definitions.
diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc
index 74124d2..b180156 100644
--- a/src/soc/amd/sabrina/Makefile.inc
+++ b/src/soc/amd/sabrina/Makefile.inc
@@ -97,10 +97,6 @@
PSP_SOFTFUSE_BITS += 7
endif
-ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y)
-PSP_SOFTFUSE_BITS += 15
-endif
-
ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y)
# Enable secure debug unlock
PSP_SOFTFUSE_BITS += 0
--
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Change subject: payloads/tianocore: Allow custom build parameters for custom builds
......................................................................
Patch Set 4: Code-Review+1
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Change subject: drivers/intel/gma/opregion.c: Fix uninitialised variable use
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/drivers/intel/gma/opregion.c:
https://review.coreboot.org/c/coreboot/+/61892/comment/e90829e4_3d598545
PS3, Line 335: opregion_size += vbt->hdr_vbt_size;
Seems like this could use a comment to the effect that we're adding space for the extended VBT header even if it's not used, since it's not obvious from the field name
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63025
to look at the new patch set (#3).
Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
......................................................................
soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
SMMINFO is already set up in S5, so it should be skipped in S3 resume
BUG=b:194990818
TEST=Build guybrush
Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/soc/amd/cezanne/cpu.c
1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/63025/3
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63034 )
Change subject: Docs/project_ideas: Make coreboot ARM BBR compliant
......................................................................
Patch Set 1:
(1 comment)
File Documentation/contributing/project_ideas.md:
https://review.coreboot.org/c/coreboot/+/63034/comment/6904f9e4_a2da6c70
PS1, Line 232: ## Make coreboot ARM (L)BBR compliant
> It would be nice if this could emphasize a bit more that this is an _optional_ alternative configuration, and it should be implemented in a way that in no way compromises the existing use cases (not even with extra bloat). "Make coreboot compliant" just sounds like there's a bug with the existing coreboot support that needs to be fixed.
Thanks for the feedback. I'll try to reflect those concerns more clearly.
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63048
to review the following change.
Change subject: vendorcode/amd/pi: Fix building with clang
......................................................................
vendorcode/amd/pi: Fix building with clang
Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/vendorcode/amd/pi/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/63048/1
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 75de398..9b4659e 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -62,6 +62,7 @@
AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include
AGESA_CFLAGS += -march=amdfam10 -mno-3dnow
+AGESA_CFLAGS += -Wno-pragma-pack
AGESA_CFLAGS += -fno-strict-aliasing -D__LIBAGESA__
CFLAGS_x86_32 += $(AGESA_CFLAGS)
CFLAGS_x86_64 += $(AGESA_CFLAGS)
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63047
to review the following change.
Change subject: vendorcode/amd/cimx/sb900: No current users in the tree
......................................................................
vendorcode/amd/cimx/sb900: No current users in the tree
Change-Id: I4374360c211593a8468b6226f3d1729885b533e0
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/amd/common/Makefile.inc
M src/vendorcode/amd/cimx/Makefile.inc
D src/vendorcode/amd/cimx/sb900/AcpiLib.c
D src/vendorcode/amd/cimx/sb900/AcpiLib.h
D src/vendorcode/amd/cimx/sb900/AmdLib.c
D src/vendorcode/amd/cimx/sb900/AmdSbLib.c
D src/vendorcode/amd/cimx/sb900/AmdSbLib.h
D src/vendorcode/amd/cimx/sb900/Azalia.c
D src/vendorcode/amd/cimx/sb900/Debug.c
D src/vendorcode/amd/cimx/sb900/Dispatcher.c
D src/vendorcode/amd/cimx/sb900/Ec.c
D src/vendorcode/amd/cimx/sb900/EcFan.h
D src/vendorcode/amd/cimx/sb900/EcFanLib.c
D src/vendorcode/amd/cimx/sb900/EcFanc.c
D src/vendorcode/amd/cimx/sb900/EcLib.c
D src/vendorcode/amd/cimx/sb900/Gec.c
D src/vendorcode/amd/cimx/sb900/Gpp.c
D src/vendorcode/amd/cimx/sb900/GppHp.c
D src/vendorcode/amd/cimx/sb900/Hudson-2.h
D src/vendorcode/amd/cimx/sb900/Hwm.c
D src/vendorcode/amd/cimx/sb900/IoLib.c
D src/vendorcode/amd/cimx/sb900/Legacy.c
D src/vendorcode/amd/cimx/sb900/Makefile.inc
D src/vendorcode/amd/cimx/sb900/MemLib.c
D src/vendorcode/amd/cimx/sb900/OEM.h
D src/vendorcode/amd/cimx/sb900/PciLib.c
D src/vendorcode/amd/cimx/sb900/Pmio2Lib.c
D src/vendorcode/amd/cimx/sb900/PmioLib.c
D src/vendorcode/amd/cimx/sb900/SBPort.c
D src/vendorcode/amd/cimx/sb900/Sata.c
D src/vendorcode/amd/cimx/sb900/SbBiosRamUsage.h
D src/vendorcode/amd/cimx/sb900/SbCmn.c
D src/vendorcode/amd/cimx/sb900/SbDef.h
D src/vendorcode/amd/cimx/sb900/SbMain.c
D src/vendorcode/amd/cimx/sb900/SbModInf.c
D src/vendorcode/amd/cimx/sb900/SbPeLib.c
D src/vendorcode/amd/cimx/sb900/SbSubFun.h
D src/vendorcode/amd/cimx/sb900/SbType.h
D src/vendorcode/amd/cimx/sb900/Smm.c
D src/vendorcode/amd/cimx/sb900/Usb.c
40 files changed, 0 insertions(+), 15,126 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/63047/1
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63045
to review the following change.
Change subject: amd/*/gcccar.inc: Remove local declarations
......................................................................
amd/*/gcccar.inc: Remove local declarations
Although useful to declare local symbols inside macros clang does not
support them. With BUILD_TIMELESS=1 the binaries don't change and do
build with GCC so nothing is lost here.
Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/vendorcode/amd/agesa/f14/gcccar.inc
M src/vendorcode/amd/agesa/f15tn/gcccar.inc
M src/vendorcode/amd/agesa/f16kb/gcccar.inc
M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
5 files changed, 0 insertions(+), 79 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/63045/1
diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc
index 95dd74d..7e0605f 100644
--- a/src/vendorcode/amd/agesa/f14/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f14/gcccar.inc
@@ -245,7 +245,6 @@
* SI[31:27]= reserved, =0
****************************************************************************/
.macro GET_NODE_ID_CORE_ID
- LOCAL node_core_exit
mov $-1, %si
GET_NODE_ID_CORE_ID_F10
@@ -297,7 +296,6 @@
# * No INVD or WBINVD, no exceptions, page faults or interrupts
****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
- LOCAL fam10_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -378,7 +376,6 @@
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
- LOCAL fam10_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -448,8 +445,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F10
- LOCAL node_core_f10_exit
- LOCAL node_core_f10_AP
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f10_exit # Br if yes
@@ -564,7 +559,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12
- LOCAL fam12_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -627,7 +621,6 @@
* * MSRC001_1029[ClflushSerialize]=0
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12
- LOCAL fam12_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -690,7 +683,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F12
- LOCAL node_core_f12_exit
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f12_exit # Br if yes
@@ -730,7 +722,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14
- LOCAL fam14_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -783,7 +774,6 @@
* * MSRC001_1022[DIS_HW_PF]=0.
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14
- LOCAL fam14_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -838,7 +828,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F14
- LOCAL node_core_f14_exit
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f14_exit # Br if yes
@@ -885,7 +874,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -946,7 +934,6 @@
* * MSRC001_1022[DIS_HW_PF]=0
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -1023,9 +1010,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F15
- LOCAL node_core_f15_exit
- LOCAL node_core_f15_AP
- LOCAL node_core_f15_shared
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f15_exit # Br if yes
@@ -1245,10 +1229,6 @@
.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
- LOCAL SetupStack
- LOCAL Real16bMode
- LOCAL Protected32Mode
- LOCAL ClearTheStack
# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
index fb49c17..a6cfd24 100644
--- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc
@@ -286,7 +286,6 @@
* SI[31:27]= reserved, =0
****************************************************************************/
.macro GET_NODE_ID_CORE_ID
- LOCAL node_core_exit
mov $-1, %si
GET_NODE_ID_CORE_ID_F10
@@ -338,7 +337,6 @@
# * No INVD or WBINVD, no exceptions, page faults or interrupts
****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
- LOCAL fam10_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -419,7 +417,6 @@
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F10
- LOCAL fam10_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -489,8 +486,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F10
- LOCAL node_core_f10_exit
- LOCAL node_core_f10_AP
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f10_exit # Br if yes
@@ -604,7 +599,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F12
- LOCAL fam12_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -667,7 +661,6 @@
* * MSRC001_1029[ClflushSerialize]=0
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F12
- LOCAL fam12_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -730,7 +723,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F12
- LOCAL node_core_f12_exit
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f12_exit # Br if yes
@@ -770,7 +762,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14
- LOCAL fam14_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -823,7 +814,6 @@
* * MSRC001_1022[DIS_HW_PF]=0.
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14
- LOCAL fam14_disable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
shr $20, %eax # AL = cpu extended family
@@ -878,7 +868,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F14
- LOCAL node_core_f14_exit
cmp $-1, %si # Has node/core already been discovered?
jnz node_core_f14_exit # Br if yes
@@ -923,7 +912,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -1047,8 +1035,6 @@
* * MSRC001_1022[DIS_HW_PF]=0
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_disable_stack_hook_exit
- LOCAL fam15_disable_stack_remote_read_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -1317,10 +1303,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F15
- LOCAL node_core_f15_exit
- LOCAL node_core_f15_AP
- LOCAL node_core_f15_shared
- LOCAL node_core_f15_AP_not_TN
#define F15_L2Size 512
#define F15_ShareCores 2
@@ -1561,10 +1543,6 @@
.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
- LOCAL SetupStack
- LOCAL Real16bMode
- LOCAL Protected32Mode
- LOCAL ClearTheStack
# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
index 9c7bf47..a34840d 100644
--- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc
+++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc
@@ -281,7 +281,6 @@
* SI[31:27]= reserved, =0
****************************************************************************/
.macro GET_NODE_ID_CORE_ID
- LOCAL node_core_exit
mov $-1, %si
GET_NODE_ID_CORE_ID_F16
@@ -335,7 +334,6 @@
*/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F16
- LOCAL fam16_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -400,9 +398,6 @@
;---------------------------------------------------
*/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F16
- LOCAL fam16_disable_stack_hook_exit
- LOCAL fam16_disable_stack_remote_read_exit
-# LOCAL fam16_invd_done_remote_read_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -722,10 +717,6 @@
*/
.macro GET_NODE_ID_CORE_ID_F16
- LOCAL node_core_f16_exit
- LOCAL node_core_f16_AP
- LOCAL node_core_f16_shared
- LOCAL node_core_f16_AP_not_TN
#define F16_L2Size 1024
#define F16_ShareCores 4
@@ -925,10 +916,6 @@
.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
- LOCAL SetupStack
- LOCAL Real16bMode
- LOCAL Protected32Mode
- LOCAL ClearTheStack
# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index 152e279..35c0fee 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -290,7 +290,6 @@
* SI[31:27]= reserved, =0
****************************************************************************/
.macro GET_NODE_ID_CORE_ID
- LOCAL node_core_exit
mov $-1, %si
//GET_NODE_ID_CORE_ID_F10
@@ -340,7 +339,6 @@
* * No INVD or WBINVD, no exceptions, page faults or interrupts
*****************************************************************************/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -415,8 +413,6 @@
* * MSRC001_1022[DIS_HW_PF]=0
*****************************************************************************/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
- LOCAL fam15_disable_stack_hook_exit
- LOCAL fam15_disable_stack_remote_read_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -703,9 +699,6 @@
*****************************************************************************/
.macro GET_NODE_ID_CORE_ID_F15
- LOCAL node_core_f15_exit
- LOCAL node_core_f15_AP
- LOCAL node_core_f15_shared
#define F15_L2Size 512
#define F15_ShareCores 2
@@ -947,10 +940,6 @@
.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
- LOCAL SetupStack
- LOCAL Real16bMode
- LOCAL Protected32Mode
- LOCAL ClearTheStack
# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index ef08c87..cfebdc2 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -281,7 +281,6 @@
* SI[31:27]= reserved, =0
****************************************************************************/
.macro GET_NODE_ID_CORE_ID
- LOCAL node_core_exit
mov $-1, %si
GET_NODE_ID_CORE_ID_F16
@@ -335,7 +334,6 @@
*/
.macro AMD_ENABLE_STACK_FAMILY_HOOK_F16
- LOCAL fam16_enable_stack_hook_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -400,9 +398,6 @@
;---------------------------------------------------
*/
.macro AMD_DISABLE_STACK_FAMILY_HOOK_F16
- LOCAL fam16_disable_stack_hook_exit
- LOCAL fam16_disable_stack_remote_read_exit
-# LOCAL fam16_invd_done_remote_read_exit
AMD_CPUID $CPUID_MODEL
mov %eax, %ebx # Save revision info to EBX
@@ -729,10 +724,6 @@
*/
.macro GET_NODE_ID_CORE_ID_F16
- LOCAL node_core_f16_exit
- LOCAL node_core_f16_AP
- LOCAL node_core_f16_shared
- LOCAL node_core_f16_AP_not_TN
#define F16_L2Size 1024
#define F16_ShareCores 4
@@ -932,10 +923,6 @@
.macro AMD_ENABLE_STACK
# These are local labels. Declared so linker doesn't cause 'redefined label' errors
- LOCAL SetupStack
- LOCAL Real16bMode
- LOCAL Protected32Mode
- LOCAL ClearTheStack
# Note that SS:ESP will be default stack. Note that this stack
# routine will not be used after memory has been initialized. Because
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I01054e2bdcb63810b21eb51b46bdc6e1bd999516
Gerrit-Change-Number: 63045
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
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