coreboot-gerrit March 2022

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Change in coreboot[master]: sb/amd/hudson/spi.c: Use C over CPP conditional
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63056 to review the following change. Change subject: sb/amd/hudson/spi.c: Use C over CPP conditional ...................................................................... sb/amd/hudson/spi.c: Use C over CPP conditional Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/amd/agesa/hudson/spi.c 1 file changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/63056/1 diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index b2f9ff2..986f094 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -97,15 +97,15 @@ readoffby1 = bytesout ? 0 : 1; -#if CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE) - spi_write(0x1E, 5); - spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - spi_write(0x1E, 6); - spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ -#else - u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; - spi_write(SPI_REG_CNTRL01, readwrite); -#endif + if (CONFIG(SOUTHBRIDGE_AMD_AGESA_YANGTZE)) { + spi_write(0x1E, 5); + spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + spi_write(0x1E, 6); + spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ + } else { + u8 readwrite = (bytesin + readoffby1) << 4 | bytesout; + spi_write(SPI_REG_CNTRL01, readwrite); + } spi_write(SPI_REG_OPCODE, cmd); reset_internal_fifo_pointer(); -- To view, visit https://review.coreboot.org/c/coreboot/+/63056 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie6e2420813e1b3e8885499b4739b1222aa1b46e6 Gerrit-Change-Number: 63056 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/*/BiosCallOuts.c: Fix unused variable
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63055 to review the following change. Change subject: mb/*/BiosCallOuts.c: Fix unused variable ...................................................................... mb/*/BiosCallOuts.c: Fix unused variable This fixes clang builds. Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/amd/inagua/BiosCallOuts.c M src/mainboard/amd/persimmon/BiosCallOuts.c M src/mainboard/amd/south_station/BiosCallOuts.c M src/mainboard/amd/union_station/BiosCallOuts.c M src/mainboard/asrock/e350m1/BiosCallOuts.c M src/mainboard/elmex/pcm205400/BiosCallOuts.c M src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c 7 files changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/63055/1 diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index 56a7f53..e7de9e3 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -28,13 +28,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; MEM_DATA_STRUCT *MemData; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; - FcnData = Data; MemData = ConfigPtr; Status = AGESA_SUCCESS; @@ -101,13 +99,11 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; UINT8 Data8; - FcnData = Data; ResetInfo = ConfigPtr; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; Status = AGESA_UNSUPPORTED; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index bee2f9e..46a3308 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -36,13 +36,11 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; UINT8 Data8; - FcnData = Data; ResetInfo = ConfigPtr; Status = AGESA_UNSUPPORTED; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 6216a3f..83f79dd 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -28,13 +28,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; MEM_DATA_STRUCT *MemData; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; - FcnData = Data; MemData = ConfigPtr; Status = AGESA_SUCCESS; @@ -101,14 +99,12 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; UINT8 Data8; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; - FcnData = Data; ResetInfo = ConfigPtr; Status = AGESA_UNSUPPORTED; switch (ResetInfo->ResetId) { diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index c324fd6..0ae60b4 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -28,13 +28,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; MEM_DATA_STRUCT *MemData; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; - FcnData = Data; MemData = ConfigPtr; Status = AGESA_SUCCESS; @@ -101,14 +99,12 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; UINT8 Data8; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; - FcnData = Data; ResetInfo = ConfigPtr; Status = AGESA_UNSUPPORTED; switch (ResetInfo->ResetId) { diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 391b308..ac42bd4 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -25,13 +25,11 @@ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; MEM_DATA_STRUCT *MemData; UINT32 GpioMmioAddr; UINT8 Data8; UINT8 TempData8; - FcnData = Data; MemData = ConfigPtr; Status = AGESA_SUCCESS; diff --git a/src/mainboard/elmex/pcm205400/BiosCallOuts.c b/src/mainboard/elmex/pcm205400/BiosCallOuts.c index bee2f9e..46a3308 100644 --- a/src/mainboard/elmex/pcm205400/BiosCallOuts.c +++ b/src/mainboard/elmex/pcm205400/BiosCallOuts.c @@ -36,13 +36,11 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - UINTN FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; UINT32 GpioMmioAddr; UINT8 Data8; - FcnData = Data; ResetInfo = ConfigPtr; Status = AGESA_UNSUPPORTED; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 64ba978..f8a48b8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -39,13 +39,11 @@ static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINTN Data, VOID *ConfigPtr) { AGESA_STATUS Status; - uint32_t FcnData; PCIe_SLOT_RESET_INFO *ResetInfo; uint32_t GpioMmioAddr; uint8_t Data8; - FcnData = Data; ResetInfo = ConfigPtr; Status = AGESA_UNSUPPORTED; GpioMmioAddr = (uintptr_t)acpimmio_gpio_100; -- To view, visit https://review.coreboot.org/c/coreboot/+/63055 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie09fae149a9530ad45f0cd5945e73f46484ef385 Gerrit-Change-Number: 63055 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/pi: Use -Wno-pragma-pack
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Fred Reitberger, Felix Held. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63054 to review the following change. Change subject: soc/amd/pi: Use -Wno-pragma-pack ...................................................................... soc/amd/pi: Use -Wno-pragma-pack Agesa headers extensively use and override pragma pack which fails to compile with clang. Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/pi/Makefile.inc 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/63054/1 diff --git a/src/soc/amd/common/pi/Makefile.inc b/src/soc/amd/common/pi/Makefile.inc index 55fbd95..8646b0b 100644 --- a/src/soc/amd/common/pi/Makefile.inc +++ b/src/soc/amd/common/pi/Makefile.inc @@ -16,4 +16,7 @@ ramstage-y += refcode_loader.c ramstage-y += s3_resume.c +CFLAGS_x86_32 += -Wno-pragma-pack +CFLAGS_x86_64 += -Wno-pragma-pack + endif # CONFIG_SOC_AMD_PI -- To view, visit https://review.coreboot.org/c/coreboot/+/63054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib234be536388f41d63c2d26cac4c35881af25930 Gerrit-Change-Number: 63054 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/pi/amd_late_init.c: Fix implicit enum conversion
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Fred Reitberger, Felix Held. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63053 to review the following change. Change subject: soc/amd/pi/amd_late_init.c: Fix implicit enum conversion ...................................................................... soc/amd/pi/amd_late_init.c: Fix implicit enum conversion This fixes building with clang. Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/pi/amd_late_init.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/63053/1 diff --git a/src/soc/amd/common/pi/amd_late_init.c b/src/soc/amd/common/pi/amd_late_init.c index 4d2250b..ea16576 100644 --- a/src/soc/amd/common/pi/amd_late_init.c +++ b/src/soc/amd/common/pi/amd_late_init.c @@ -36,8 +36,9 @@ dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->MemoryType, - dmi17->FormFactor); + dimm->mod_type = smbios_form_factor_to_spd_mod_type( + (smbios_memory_type)dmi17->MemoryType, + (smbios_memory_form_factor)dmi17->FormFactor); dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, dmi17->DataWidth); -- To view, visit https://review.coreboot.org/c/coreboot/+/63053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda9be8996703b06fe9ee30ffb5f56a91629e065 Gerrit-Change-Number: 63053 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/*/meminit.c: Fix formatted print
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63052 to review the following change. Change subject: soc/intel/*/meminit.c: Fix formatted print ...................................................................... soc/intel/*/meminit.c: Fix formatted print This fixes building with clang. Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/elkhartlake/meminit.c M src/soc/intel/jasperlake/meminit.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/63052/1 diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index d6de9a4..fd64c7d 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -12,7 +12,7 @@ { size_t spd_index = spd_info->spd_spec.spd_index; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + printk(BIOS_DEBUG, "SPD INDEX = %zu\n", spd_index); /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); diff --git a/src/soc/intel/jasperlake/meminit.c b/src/soc/intel/jasperlake/meminit.c index 9ec1ffa..9cf5ecb 100644 --- a/src/soc/intel/jasperlake/meminit.c +++ b/src/soc/intel/jasperlake/meminit.c @@ -12,7 +12,7 @@ { size_t spd_index = spd_info->spd_spec.spd_index; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + printk(BIOS_DEBUG, "SPD INDEX = %zu\n", spd_index); /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); -- To view, visit https://review.coreboot.org/c/coreboot/+/63052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Gerrit-Change-Number: 63052 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/dmi.c: Fix implicit enum typing
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Arthur Heymans, Fred Reitberger, Felix Held. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63051 to review the following change. Change subject: soc/amd/dmi.c: Fix implicit enum typing ...................................................................... soc/amd/dmi.c: Fix implicit enum typing Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/fsp/dmi.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/63051/1 diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index 64a5685..5596f97 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -52,8 +52,9 @@ dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->MemoryType, - dmi17->FormFactor); + dimm->mod_type = smbios_form_factor_to_spd_mod_type( + (smbios_memory_type)dmi17->MemoryType, + (smbios_memory_form_factor)dmi17->FormFactor); dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, dmi17->DataWidth); -- To view, visit https://review.coreboot.org/c/coreboot/+/63051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Gerrit-Change-Number: 63051 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/noncar/memmap.c: Fix formatted print
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63050 to review the following change. Change subject: soc/amd/noncar/memmap.c: Fix formatted print ...................................................................... soc/amd/noncar/memmap.c: Fix formatted print Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/noncar/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/63050/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 8f37f1a..6e35003 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -64,5 +64,5 @@ { *start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE); *size = CONFIG_ACPI_BERT_SIZE; - printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size); + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Gerrit-Change-Number: 63050 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/smmstore: Move SMMSTORE block size to Kconfig
by Sean Rhodes (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Patrick Rudolph, Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62990 to look at the new patch set (#2). Change subject: drivers/smmstore: Move SMMSTORE block size to Kconfig ...................................................................... drivers/smmstore: Move SMMSTORE block size to Kconfig Move the block size for SMMSTORE to Kconfig whilst retaining the default value of 64KiB. 64KiB is correct for 99% of implementations and should not be changed. One known exception is Apollo Lake SOC's that use 8MiB SPI's, as it's not possible to align SMMSTORE to 64KiB. In the case, the block size is changed to 4KiB. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 --- M src/drivers/smmstore/Kconfig M src/include/smmstore.h 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/62990/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieeed9f5895b8ddde753ebf596b803e8f440d5b74 Gerrit-Change-Number: 62990 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina: update soft fuse bit 15 definition
by Raul Rangel (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63049 ) Change subject: soc/amd/sabrina: update soft fuse bit 15 definition ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Gerrit-Change-Number: 63049 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 22:31:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/vboot: Fix include paths fixup macro
by Julius Werner (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jakub Czapiga. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63002 ) Change subject: libpayload/vboot: Fix include paths fixup macro ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Gerrit-Change-Number: 63002 Gerrit-PatchSet: 2 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 22:26:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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