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Change subject: ec/google: Notify DPTF driver power participant on PD event
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
Patchset:
PS4:
> I think this change should swap places with the one below it, because the one below depends on the E […]
yes, for buildbot, it won't compliant. but if you run on real device, it will failed.
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Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360
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Patch Set 4: Code-Review+2
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Change subject: mb/google/brya/var/banshee: Add mic mute switch setting
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Patch Set 8: Code-Review+2
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Change subject: soc/intel/alderlake: Enable FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Great idea. This is what I want.
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Hello build bot (Jenkins), Kangheui Won, Reka Norman, Tim Wawrzynczak, Christian Walter,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63011
to look at the new patch set (#6).
Change subject: drivers/i2c/tpm: Add workaround for Ti50 with FW under 0.15
......................................................................
drivers/i2c/tpm: Add workaround for Ti50 with FW under 0.15
Ti50 FW under 0.15 is not support board cfg command which causes I2C
errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed.
Add workaround for the old Ti50 chip.
BUG=b:224650720
TEST=no I2C errors in coreboot.
[ERROR] cr50_i2c_read: Address write failed
[INFO ] .I2C stop bit not received
Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com>
Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d
---
M src/drivers/i2c/tpm/Kconfig
M src/drivers/i2c/tpm/cr50.c
M src/mainboard/google/brya/Kconfig
3 files changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63011/6
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Change subject: drivers/i2c/tpm: Add workaround for Ti50
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63011/comment/2627c9bc_841c9176
PS4, Line 7: drivers/i2c/tpm: Add workaround for Ti50
> Maybe: […]
Done
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Change subject: amdfwtool: Add ISH header support for A/B recovery layout
......................................................................
Patch Set 65:
(1 comment)
Patchset:
PS65:
apart from the open TODO, the patch looks good to me
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Change subject: drivers/i2c/tpm: Add workaround for Ti50
......................................................................
Patch Set 4:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63011/comment/82e7f647_1c29559e
PS4, Line 9: is not support board cfg
> I do not understand the problem. Can you please elaborate. […]
this is what it's meaning. FW 0.15 and above is support board cfg, and vice versa.
https://review.coreboot.org/c/coreboot/+/63011/comment/807036f5_572c8f36
PS4, Line 11:
> What is with the firmware versions inbetween?
all under 0.15...
File src/drivers/i2c/tpm/Kconfig:
https://review.coreboot.org/c/coreboot/+/63011/comment/be0506e7_c8fe2646
PS4, Line 31: which
> with?
Done
https://review.coreboot.org/c/coreboot/+/63011/comment/3cc7b46a_81360e1f
PS4, Line 31: Board has a Ti50 I2C workaround which Ti50 FW under 0.15
> Please elaborate.
Done
File src/drivers/i2c/tpm/cr50.c:
https://review.coreboot.org/c/coreboot/+/63011/comment/362ca1eb_86235506
PS4, Line 503: /* Ti50 FW version under 0.15 doesn't support board cfg
> … anymore?
no more.
https://review.coreboot.org/c/coreboot/+/63011/comment/e2511e0c_d4205f71
PS4, Line 505: */
> Belongs on the line above.
Done
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Change subject: arch/arm: Fix assembling files with clang
......................................................................
Patch Set 1:
(4 comments)
Patchset:
PS1:
Are we trying to do clang again? I thought we figured out it was a lost cause last time?
File src/arch/arm/libgcc/lib1funcs.S:
https://review.coreboot.org/c/coreboot/+/63058/comment/0da25a91_066ab7fc
PS1, Line 70: movne \curbit, \curbit, lsr #4 @ No, any more bits to do?
Are you trying to copy what 'ARM: 8844/1: use unified assembler in assembly files' did in Linux? That just replaced the MOVNES with MOVSNE, which is just a different syntax for the same instruction. But you're actually removing the S bit and turning this into a different instruction here, which would break the code.
File src/arch/arm/memset.S:
https://review.coreboot.org/c/coreboot/+/63058/comment/7cbebe0c_20610627
PS1, Line 46:
Should still use tabs to align like the rest of the code.
https://review.coreboot.org/c/coreboot/+/63058/comment/cede5a9b_fad23c8f
PS1, Line 111: strle r1, [ip], #1 @ 1
This is changing the instruction too.
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Change subject: device/dram/common.h: Use C over CPP
......................................................................
Patch Set 1:
(1 comment)
File src/include/device/dram/common.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144604):
https://review.coreboot.org/c/coreboot/+/63057/comment/5699b0e5_4eef1151
PS1, Line 43: #define printram(x, ...) \
do {} while (0) macros should not be semicolon terminated
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