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Change subject: soc/mediatek: Add mtk_early_init for passing data across sessions
......................................................................
Patch Set 1:
(1 comment)
File src/soc/mediatek/common/early_init.c:
https://review.coreboot.org/c/coreboot/+/63019/comment/8ec52dd0_f834f480
PS1, Line 25: void mtk_pcie_save_timestamp(void)
Will it better if we move these pcie function to common/pcie.c?
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Change subject: arch/arm: Fix assembling files with clang
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > Are we trying to do clang again? I thought we figured out it was a lost cause last time? […]
I mean, feel free to try it out and if it happens to work I guess there's no harm in offering the option. I just think I recall there were more issues with clang, maybe things have changed now. We sometimes have to rely on some pretty specific GCC extensions to make things work well the way we need them, and while I think clang is compatible to most of those, if there are cases where it isn't I'd rather stick to being GCC only than have to resort to inferior solutions to allow clang support.
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Change subject: security/tpm/crtm.c: Remove set but unused variable
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/*: Use __fallthrough statement
......................................................................
Patch Set 1: Code-Review+2
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Change subject: amdfwtool: Add support for AMD's BIOS recovery feature
......................................................................
Patch Set 49:
(3 comments)
File util/amdfwtool/amdfwtool.c:
https://review.coreboot.org/c/coreboot/+/57131/comment/c1863f1e_b0f974bc
PS49, Line 587: uint32_t index;
:
: index = 0;
i'd combine those two lines into uint32_t index = 0;
https://review.coreboot.org/c/coreboot/+/57131/comment/d65e3ebc_c87e7515
PS49, Line 592: break;
you could do a return index instead of the break here and replace the if/else construct in lines 596-599 with a return -1, since there's no other code after that
https://review.coreboot.org/c/coreboot/+/57131/comment/cca35563_b080736a
PS49, Line 1899: 0x20000
should this be TABLE_ALIGNMENT?
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Change subject: drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15
......................................................................
Patch Set 7:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63011/comment/0ea61c87_848da272
PS4, Line 7: drivers/i2c/tpm: Add workaround for Ti50
> I agree that Paul's suggestion would be clearer. Maybe: […]
Done
Patchset:
PS7:
Thank you, Reka.
File src/drivers/i2c/tpm/Kconfig:
https://review.coreboot.org/c/coreboot/+/63011/comment/b675748e_ad57736d
PS4, Line 31: Board has a Ti50 I2C workaround which Ti50 FW under 0.15
> I agree we could add some more details here. Maybe something like: […]
Done
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Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
Patch Set 1:
(4 comments)
File src/soc/sifive/fu540/ux00ddr.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144623):
https://review.coreboot.org/c/coreboot/+/63074/comment/f8eb3e01_3904907c
PS1, Line 179: /* char slicelsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144623):
https://review.coreboot.org/c/coreboot/+/63074/comment/5ed3b7b3_7e355218
PS1, Line 180: /* char slicemsc = '0'; */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144623):
https://review.coreboot.org/c/coreboot/+/63074/comment/fff0c38d_35e7b1a4
PS1, Line 181: /* slicelsc += (dq % 10); */
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144623):
https://review.coreboot.org/c/coreboot/+/63074/comment/40342864_4cbb8729
PS1, Line 182: /* slicemsc += (dq / 10); */
code indent should use tabs where possible
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Change subject: drivers/i2c/tpm: Add workaround for Ti50 with FW under 0.15
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/63011/comment/8ddb54b8_247e848f
PS4, Line 7: drivers/i2c/tpm: Add workaround for Ti50
> Done
I agree that Paul's suggestion would be clearer. Maybe:
```
Work around missing board_cfg in Ti50 FW under 0.15
```
File src/drivers/i2c/tpm/Kconfig:
https://review.coreboot.org/c/coreboot/+/63011/comment/539a3775_fbd96e93
PS4, Line 31: Board has a Ti50 I2C workaround which Ti50 FW under 0.15
> Done
I agree we could add some more details here. Maybe something like:
```
Ti50 FW versions below 0.15 don't support the firmware_version or board_cfg registers, and trying to access them causes I2C errors. This config will skip accesses to these registers, and should be selected for boards using Ti50 chips with FW < 0.15. The config will be removed once all Ti50 stocks are updated to 0.15 or higher.
```
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Change subject: arch/arm: Fix assembling files with clang
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
> Are we trying to do clang again? I thought we figured out it was a lost cause last time?
Not sure who tried last time, but in the mean time things improved. I think the Linux kernel can properly build on some arch with clang now although arm might be an exception. With coreboot it seems to work well for x86. On other arch the compiler is confused because the flags don't align as well with gcc. Maybe for arm the sane thing to do is to depend on CONFIG_COMPILER_GCC and drop this?
File src/arch/arm/libgcc/lib1funcs.S:
https://review.coreboot.org/c/coreboot/+/63058/comment/c5f2da88_4ae818e5
PS1, Line 70: movne \curbit, \curbit, lsr #4 @ No, any more bits to do?
> Are you trying to copy what 'ARM: 8844/1: use unified assembler in assembly files' did in Linux? That just replaced the MOVNES with MOVSNE, which is just a different syntax for the same instruction. But you're actually removing the S bit and turning this into a different instruction here, which would break the code.
Sorry I was not very careful with this CL. I should have marked it WIP and check that it's binary identical.
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63074
to review the following change.
Change subject: soc/sifive/ux00ddr.h: Remove set but unused variables
......................................................................
soc/sifive/ux00ddr.h: Remove set but unused variables
It looks like this code was not finished so it's left commented out
for now.
Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/sifive/fu540/ux00ddr.h
1 file changed, 4 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/63074/1
diff --git a/src/soc/sifive/fu540/ux00ddr.h b/src/soc/sifive/fu540/ux00ddr.h
index cc67508..bf856f3 100644
--- a/src/soc/sifive/fu540/ux00ddr.h
+++ b/src/soc/sifive/fu540/ux00ddr.h
@@ -176,10 +176,10 @@
if (failc0 || failc1) {
//if (fails==0) uart_puts((void*) UART0_CTRL_ADDR, "DDR error in fixing up \n");
fails |= (1<<dq);
- char slicelsc = '0';
- char slicemsc = '0';
- slicelsc += (dq % 10);
- slicemsc += (dq / 10);
+ /* char slicelsc = '0'; */
+ /* char slicemsc = '0'; */
+ /* slicelsc += (dq % 10); */
+ /* slicemsc += (dq / 10); */
//uart_puts((void*) UART0_CTRL_ADDR, "S ");
//uart_puts((void*) UART0_CTRL_ADDR, &slicemsc);
//uart_puts((void*) UART0_CTRL_ADDR, &slicelsc);
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