coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

1 participants
6700 discussions

Change in coreboot[master]: arch/riscv: Use updated name for sbadaddr
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Philipp Hug, Arthur Heymans, ron minnich. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63073 to review the following change. Change subject: arch/riscv: Use updated name for sbadaddr ...................................................................... arch/riscv: Use updated name for sbadaddr The riscv spec v1.10.0 updated this name. This fixes building with clang. Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/trap_handler.c M src/arch/riscv/trap_util.S 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/63073/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index f940f63..a3aad48 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -150,7 +150,7 @@ /* This function used to redirect trap to s-mode. */ void redirect_trap(void) { - write_csr(sbadaddr, read_csr(mbadaddr)); + write_csr(mtval, read_csr(mtval)); write_csr(sepc, read_csr(mepc)); write_csr(scause, read_csr(mcause)); write_csr(mepc, read_csr(stvec)); diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index f1c4c4d..c106d5b 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -80,7 +80,7 @@ csrrw t0,mscratch,x0 csrr s0,mstatus csrr t1,mepc - csrr t2,mbadaddr + csrr t2,mtval csrr t3,mcause STORE t0,2*REGBYTES(x2) STORE s0,32*REGBYTES(x2) -- To view, visit https://review.coreboot.org/c/coreboot/+/63073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic86e5070b084bf1ce03fe30d46abbbd0c88b9532 Gerrit-Change-Number: 63073 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: arch/riscv/mcall.h: Fix building with clang
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Philipp Hug, Arthur Heymans, ron minnich. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63072 to review the following change. Change subject: arch/riscv/mcall.h: Fix building with clang ...................................................................... arch/riscv/mcall.h: Fix building with clang Having multiple statements hidden inside a macro that supposedly returns a pointer does not work well with clang. Moving the stack register to a global variable fixes this. Change-Id: If24b2766404b892a006926f0cd45771ceebf1275 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/include/mcall.h 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/63072/1 diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h index 803ee3e..12483ca 100644 --- a/src/arch/riscv/include/mcall.h +++ b/src/arch/riscv/include/mcall.h @@ -54,9 +54,10 @@ sizeof(hls_t) == HLS_SIZE, "HLS_SIZE must equal to sizeof(hls_t)"); -#define MACHINE_STACK_TOP() ({ \ +register uintptr_t sp asm("sp"); + +#define MACHINE_STACK_TOP() ({ \ /* coverity[uninit_use] : FALSE */ \ - register uintptr_t sp asm ("sp"); \ (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) // hart-local storage, at top of stack -- To view, visit https://review.coreboot.org/c/coreboot/+/63072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If24b2766404b892a006926f0cd45771ceebf1275 Gerrit-Change-Number: 63072 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: nb/intel/snb/raminit_mrc.c: Remove set but unused variable
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Angel Pons, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63071 to review the following change. Change subject: nb/intel/snb/raminit_mrc.c: Remove set but unused variable ...................................................................... nb/intel/snb/raminit_mrc.c: Remove set but unused variable Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/63071/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index fbb2b6e..2693afb 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -392,7 +392,7 @@ void setup_sdram_meminfo(struct pei_data *pei_data) { - u32 addr_decoder_common, addr_decode_ch[2]; + u32 addr_decode_ch[2]; struct memory_info *mem_info; struct dimm_info *dimm; int dimm_size; @@ -402,7 +402,6 @@ mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); memset(mem_info, 0, sizeof(struct memory_info)); - addr_decoder_common = mchbar_read32(MAD_CHNL); addr_decode_ch[0] = mchbar_read32(MAD_DIMM_CH0); addr_decode_ch[1] = mchbar_read32(MAD_DIMM_CH1); -- To view, visit https://review.coreboot.org/c/coreboot/+/63071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1cf656b404b0e880c061b273ef259ca40a6d499a Gerrit-Change-Number: 63071 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: security/tpm/crtm.c: Remove set but unused variable
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Christian Walter, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63070 to review the following change. Change subject: security/tpm/crtm.c: Remove set but unused variable ...................................................................... security/tpm/crtm.c: Remove set but unused variable Change-Id: I3c97cb57fe13adee217783973691748d6c542abe Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/security/tpm/tspi/crtm.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/63070/1 diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index 8cd0793..2d0901d 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -140,7 +140,6 @@ int tspi_measure_cache_to_pcr(void) { int i; - enum vb2_hash_algorithm hash_alg; struct tcpa_table *tclt = tcpa_log_init(); /* This means the table is empty. */ @@ -151,11 +150,6 @@ printk(BIOS_WARNING, "TCPA: Log non-existent!\n"); return VB2_ERROR_UNKNOWN; } - if (CONFIG(TPM1)) { - hash_alg = VB2_HASH_SHA1; - } else { /* CONFIG_TPM2 */ - hash_alg = VB2_HASH_SHA256; - } printk(BIOS_DEBUG, "TPM: Write digests cached in TCPA log to PCR\n"); for (i = 0; i < tclt->num_entries; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/63070 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c97cb57fe13adee217783973691748d6c542abe Gerrit-Change-Number: 63070 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/denverton_ns: Remove always false statement
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jeff Daly, Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63069 to review the following change. Change subject: soc/intel/denverton_ns: Remove always false statement ...................................................................... soc/intel/denverton_ns: Remove always false statement This fixes building with clang. Change-Id: I7405f031298a35589e435e888af911d916662d23 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/denverton_ns/romstage.c 1 file changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/63069/1 diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index c7d2093..2f3a5cc 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -158,12 +158,6 @@ die("HSIO Configuration is invalid, please correct " "it!"); - /* Check the requested FIA MUX Configuration */ - if (!(&hsio_config->FiaConfig)) { - die("Requested FIA MUX Configuration is invalid," - " please correct it!"); - } - mupd->FspmConfig.PcdHsioLanesNumber = (uint32_t)hsio_config->NumLanesSupported; mupd->FspmConfig.PcdFiaMuxConfigPtr = -- To view, visit https://review.coreboot.org/c/coreboot/+/63069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7405f031298a35589e435e888af911d916662d23 Gerrit-Change-Number: 63069 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/*: Use __fallthrough statement
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Julius Werner, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63068 to review the following change. Change subject: soc/*: Use __fallthrough statement ...................................................................... soc/*: Use __fallthrough statement Clang needs an attribute not a comment. Change-Id: I78f87d80bd4f366ed6cfa74619dd107ac61bc935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/nvidia/tegra210/bootblock.c M src/soc/rockchip/rk3288/display.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/63068/1 diff --git a/src/soc/nvidia/tegra210/bootblock.c b/src/soc/nvidia/tegra210/bootblock.c index 1657d7c..e8c4324 100644 --- a/src/soc/nvidia/tegra210/bootblock.c +++ b/src/soc/nvidia/tegra210/bootblock.c @@ -137,7 +137,7 @@ break; case OP_UDELAY: udelay(wa_op->val); - /* fall thru */ + __fallthrough; default: continue; } diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 19a75de..9d6cca1 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -63,7 +63,7 @@ if (conf->vop_mode == VOP_MODE_EDP) return; } - /* fall thru */ + __fallthrough; case VOP_MODE_HDMI: printk(BIOS_DEBUG, "Attempting to setup HDMI display.\n"); rkclk_configure_hdmi(); @@ -78,7 +78,7 @@ if (conf->vop_mode == VOP_MODE_HDMI) return; } - /* fall thru */ + __fallthrough; default: printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n"); return; -- To view, visit https://review.coreboot.org/c/coreboot/+/63068 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78f87d80bd4f366ed6cfa74619dd107ac61bc935 Gerrit-Change-Number: 63068 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: *.h: Fix up typos in guarding
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Philipp Hug, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, ron minnich, Tim Chu. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63067 to review the following change. Change subject: *.h: Fix up typos in guarding ...................................................................... *.h: Fix up typos in guarding Clang complains about this. Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/riscv/include/arch/barrier.h M src/mainboard/intel/dcp847ske/thermal.h M src/mainboard/intel/dcp847ske/usb.h M src/soc/intel/xeon_sp/include/soc/itss.h 4 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/63067/1 diff --git a/src/arch/riscv/include/arch/barrier.h b/src/arch/riscv/include/arch/barrier.h index 023e8c3..265aa22 100644 --- a/src/arch/riscv/include/arch/barrier.h +++ b/src/arch/riscv/include/arch/barrier.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -#ifndef __ARCH_BARRIER_H_ +#ifndef __ARCH_BARRIER_H__ #define __ARCH_BARRIER_H__ static inline void mb(void) { asm volatile("fence"); } diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h index fcfe695..62bfa1f 100644 --- a/src/mainboard/intel/dcp847ske/thermal.h +++ b/src/mainboard/intel/dcp847ske/thermal.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef DCP847SKE_THERMAL_H -#define DPC847SKE_THERMAL_H +#define DCP847SKE_THERMAL_H /* TODO: These should be generated at runtime from * MSR_TEMPERATURE_TARGET (0x1a2) */ diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h index 0787ed3..2469309 100644 --- a/src/mainboard/intel/dcp847ske/usb.h +++ b/src/mainboard/intel/dcp847ske/usb.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef DCP847SKE_USB_H -#define DPC847SKE_USB_H +#define DCP847SKE_USB_H USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */ USB_CONFIG(1, 1, 0), /* back, towards power plug */ diff --git a/src/soc/intel/xeon_sp/include/soc/itss.h b/src/soc/intel/xeon_sp/include/soc/itss.h index 770a7dd..3be9b8b 100644 --- a/src/soc/intel/xeon_sp/include/soc/itss.h +++ b/src/soc/intel/xeon_sp/include/soc/itss.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #ifndef SOC_INTEL_XEON_SP_ITSS_H -#define SOC_INTEL_XEONS_P_ITSS_H +#define SOC_INTEL_XEON_SP_ITSS_H #define ITSS_MAX_IRQ 119 #define IRQS_PER_IPC 32 -- To view, visit https://review.coreboot.org/c/coreboot/+/63067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I421d6c5daa373d1537e4ac2243438e7f1f6208d1 Gerrit-Change-Number: 63067 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: soc/intel/tigerlake/meminit.c: Fix clang static asserts
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Tim Wawrzynczak, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63066 to review the following change. Change subject: soc/intel/tigerlake/meminit.c: Fix clang static asserts ...................................................................... soc/intel/tigerlake/meminit.c: Fix clang static asserts Clang does not like static asserts on integral constant expressions. Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/tigerlake/meminit.c 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/63066/1 diff --git a/src/soc/intel/tigerlake/meminit.c b/src/soc/intel/tigerlake/meminit.c index e8c7b68..f90c134 100644 --- a/src/soc/intel/tigerlake/meminit.c +++ b/src/soc/intel/tigerlake/meminit.c @@ -121,7 +121,8 @@ const size_t upd_size = sizeof(mem_cfg->DqMapCpu2DramMc0Ch0); - _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH, "Incorrect DQ UPD size!"); + _Static_assert(sizeof(mem_cfg->DqMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH, + "Incorrect DQ UPD size!"); mem_init_dq_dqs_upds(dq_upds, mb_cfg->dq_map, upd_size, data); } @@ -142,7 +143,8 @@ const size_t upd_size = sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0); - _Static_assert(upd_size == CONFIG_MRC_CHANNEL_WIDTH / 8, "Incorrect DQS UPD size!"); + _Static_assert(sizeof(mem_cfg->DqsMapCpu2DramMc0Ch0) == CONFIG_MRC_CHANNEL_WIDTH / 8, + "Incorrect DQS UPD size!"); mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5890a357ed95153d8ae2efa727c111b05bc6455 Gerrit-Change-Number: 63066 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: drivers/intel/fsp1_1: Use C over CPP
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Lee Leahy, Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63065 to review the following change. Change subject: drivers/intel/fsp1_1: Use C over CPP ...................................................................... drivers/intel/fsp1_1: Use C over CPP This fixes building with clang. Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/intel/fsp1_1/fsp_util.c 1 file changed, 19 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/63065/1 diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 7dc16c3..1c205ae 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -89,26 +89,26 @@ (u8)((fsp_header->ImageRevision >> 16) & 0xff), (u8)((fsp_header->ImageRevision >> 8) & 0xff), (u8)(fsp_header->ImageRevision & 0xff)); -#if CONFIG(DISPLAY_FSP_ENTRY_POINTS) - printk(BIOS_SPEW, "FSP Entry Points:\n"); - printk(BIOS_SPEW, " %p: Image Base\n", fsp_base); - printk(BIOS_SPEW, " %p: TempRamInit\n", - &fsp_base[fsp_header->TempRamInitEntryOffset]); - printk(BIOS_SPEW, " %p: FspInit\n", - &fsp_base[fsp_header->FspInitEntryOffset]); - if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) { - printk(BIOS_SPEW, " %p: MemoryInit\n", - &fsp_base[fsp_header->FspMemoryInitEntryOffset]); - printk(BIOS_SPEW, " %p: TempRamExit\n", - &fsp_base[fsp_header->TempRamExitEntryOffset]); - printk(BIOS_SPEW, " %p: SiliconInit\n", - &fsp_base[fsp_header->FspSiliconInitEntryOffset]); + if (CONFIG(DISPLAY_FSP_ENTRY_POINTS)) { + printk(BIOS_SPEW, "FSP Entry Points:\n"); + printk(BIOS_SPEW, " %p: Image Base\n", fsp_base); + printk(BIOS_SPEW, " %p: TempRamInit\n", + &fsp_base[fsp_header->TempRamInitEntryOffset]); + printk(BIOS_SPEW, " %p: FspInit\n", + &fsp_base[fsp_header->FspInitEntryOffset]); + if (fsp_header->HeaderRevision >= FSP_HEADER_REVISION_2) { + printk(BIOS_SPEW, " %p: MemoryInit\n", + &fsp_base[fsp_header->FspMemoryInitEntryOffset]); + printk(BIOS_SPEW, " %p: TempRamExit\n", + &fsp_base[fsp_header->TempRamExitEntryOffset]); + printk(BIOS_SPEW, " %p: SiliconInit\n", + &fsp_base[fsp_header->FspSiliconInitEntryOffset]); + } + printk(BIOS_SPEW, " %p: NotifyPhase\n", + &fsp_base[fsp_header->NotifyPhaseEntryOffset]); + printk(BIOS_SPEW, " %p: Image End\n", + &fsp_base[fsp_header->ImageSize]); } - printk(BIOS_SPEW, " %p: NotifyPhase\n", - &fsp_base[fsp_header->NotifyPhaseEntryOffset]); - printk(BIOS_SPEW, " %p: Image End\n", - &fsp_base[fsp_header->ImageSize]); -#endif } void fsp_notify(u32 phase) -- To view, visit https://review.coreboot.org/c/coreboot/+/63065 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida464d9ff96af3ff485682fbbf904bb2253ec44f Gerrit-Change-Number: 63065 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Kconfig: Have CONFIG_ASAN depend on COMPILER_GCC
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63064 to review the following change. Change subject: Kconfig: Have CONFIG_ASAN depend on COMPILER_GCC ...................................................................... Kconfig: Have CONFIG_ASAN depend on COMPILER_GCC -fsanitize=kernel-address is not implemented in clang Change-Id: Ib8660bf99b940ff9eac7461f5946df0891dd3a4f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/63064/1 diff --git a/src/Kconfig b/src/Kconfig index d57ce90..3811efc 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -312,6 +312,7 @@ default n select ASAN_IN_ROMSTAGE if HAVE_ASAN_IN_ROMSTAGE select ASAN_IN_RAMSTAGE if HAVE_ASAN_IN_RAMSTAGE + depends on COMPILER_GCC help Enable address sanitizer - runtime memory debugger, designed to find out-of-bounds accesses and use-after-scope bugs. -- To view, visit https://review.coreboot.org/c/coreboot/+/63064 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8660bf99b940ff9eac7461f5946df0891dd3a4f Gerrit-Change-Number: 63064 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2022