coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mb/google/brya/var/gimble: Include 4 new SPDs
by Mark Hsieh (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: YH Lin, Furquan Shaikh, Paul Menzel, Angel Pons, Nick Vaccaro, Zhuohao Lee, Felix Held. Mark Hsieh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62991 ) Change subject: mb/google/brya/var/gimble: Include 4 new SPDs ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62991/comment/53bb829e_50f249da PS1, Line 9: Add SPDs support to gimble for LPDDR4 memory part H54G56CYRBX247 : H54G46CYRBX267, K4UBE3D4AB-MGCL and K4U6E3S4AB-MGCL. > If you could also add the vendor, that’d be great. Updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/62991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Gerrit-Change-Number: 62991 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 01:50:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/gimble: Include 4 new SPDs
by Mark Hsieh (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: YH Lin, Furquan Shaikh, Angel Pons, Nick Vaccaro, Mark Hsieh, Zhuohao Lee, Felix Held. Hello build bot (Jenkins), YH Lin, Furquan Shaikh, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Zhuohao Lee, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62991 to look at the new patch set (#2). Change subject: mb/google/brya/var/gimble: Include 4 new SPDs ...................................................................... mb/google/brya/var/gimble: Include 4 new SPDs Add the four SPD files for LPDDD4 memory parts below to gimble: 1. Hynix H54G56CYRBX247 2. Hynix H54G46CYRBX267 3. Samsung K4UBE3D4AB-MGCL 4. Samsung K4U6E3S4AB-MGCL BUG=b:191574298 TEST=USE="project_gimble emerge-brya coreboot" Signed-off-by: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Change-Id: I143207cda066603051803b9008eb2e2364f16e46 --- M src/mainboard/google/brya/variants/gimble/memory/Makefile.inc M src/mainboard/google/brya/variants/gimble/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/gimble/memory/mem_parts_used.txt 3 files changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/62991/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I143207cda066603051803b9008eb2e2364f16e46 Gerrit-Change-Number: 62991 Gerrit-PatchSet: 2 Gerrit-Owner: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Ariel Fang <ariel_fang(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Terry Chen <terry_chen(a)wistron.corp-partner.google.com> Gerrit-Attention: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: $top/Makefile.inc: Move common folder before other sibling ones
by Bao Zheng (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Marshall Dawson, Paul Menzel, Julius Werner, Zheng Bao, Elyes Haouas, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62750 ) Change subject: $top/Makefile.inc: Move common folder before other sibling ones ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62750/comment/0e979154_60807f19 PS3, Line 13: The duplicated "common" in the result string can be eliminated finally. > I think it would be better to solve this globally rather than hack in filter commands everywhere it […] The original intention is put folder common before others. The command sort would reorder the subdirs and "common" would be placed after the siblings. -- To view, visit https://review.coreboot.org/c/coreboot/+/62750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Gerrit-Change-Number: 62750 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <martinroth(a)google.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 23 Mar 2022 01:28:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/i2c/tpm: Add workaround for Ti50
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Eric Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63011 ) Change subject: drivers/i2c/tpm: Add workaround for Ti50 ...................................................................... drivers/i2c/tpm: Add workaround for Ti50 Ti50 FW under 0.15 is not support board cfg. And ODM stocks are 0.12 pre-flashed. Add workaroud for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d --- M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/cr50.c M src/mainboard/google/brya/Kconfig 3 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/63011/1 diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index dcf9060..61e9c80 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -24,6 +24,12 @@ help Board has a generic I2C TPM support +config MAINBOARD_HAS_I2C_TI50 + bool + default n + help + Board has a Ti50 I2C TPM support + config DRIVER_TIS_DEFAULT bool depends on I2C_TPM diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index ce2278b..726dfa7 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -500,7 +500,10 @@ printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", bus, dev_addr, did_vid >> 16); - if (tpm_first_access_this_boot()) { + /* Ti50 FW version under 0.15 doesn't support board cfg + TODO: remove this flag after all stocks Ti50 uprev to 0.15 or above + */ + if (!CONFIG(MAINBOARD_HAS_I2C_TI50) && tpm_first_access_this_boot()) { /* This is called for the side-effect of printing the version string. */ cr50_get_firmware_version(&ver); cr50_set_board_cfg(); diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 199db11..0139d54 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -60,6 +60,7 @@ def_bool n select BOARD_GOOGLE_BRYA_COMMON select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select MAINBOARD_HAS_I2C_TI50 select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 1 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/brya0: Replace amp max98357 with max98360
by Eric Lai (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Frank Wu, Amanda Hwang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62998 ) Change subject: mb/google/brya/var/brya0: Replace amp max98357 with max98360 ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Will this broken the OEM string, looks like a little long? try dmidecode to see the OEM string -- To view, visit https://review.coreboot.org/c/coreboot/+/62998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3033e31cf5c2dade02dc19531f5e5365eeeb7a78 Gerrit-Change-Number: 62998 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Wed, 23 Mar 2022 00:27:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add a mutex
by Julius Werner (Code Review) 23 Mar '22

23 Mar '22

Attention is currently required from: Raul Rangel, Nico Huber, Xiang W, Philipp Hug, Jonathan Neuschäfer, Tim Wawrzynczak, Angel Pons, Kyösti Mälkki, Rob Barnes, Karthik Ramasubramanian. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59320 ) Change subject: lib: Add a mutex ...................................................................... Patch Set 15: Code-Review+2 (2 comments) Patchset: PS15: > Oops, sorry: https://source.chromium. […] So is there still any actual concern here about riscv? I see they have custom atomic implementations in the code but I don't see why this generic version wouldn't work just as well. The atomic built-ins are implemented for RISC-V by GCC (it writes an AMOOR instruction for the test-and-set which seems to have the right semantics). Adding some people who implemented the riscv code for comment. PS15: Well, I'm not sure what more to say here. I've tried to explain in detail why I think this simplification is harmless and useful in earlier comments but nobody really responded to that. I still think this is the right direction so if there are no more hard objections I will give a +2 now. -- To view, visit https://review.coreboot.org/c/coreboot/+/59320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I41e02a54a17b1f6513b36a0274e43fc715472d78 Gerrit-Change-Number: 59320 Gerrit-PatchSet: 15 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Xiang W <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Xiang W <wxjstz(a)126.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 22 Mar 2022 23:17:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in blobs[master]: mb/google/guybrush: Update APCB file
by Karthik Ramasubramanian (Code Review) 23 Mar '22

23 Mar '22

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/blobs/+/62963 ) Change subject: mb/google/guybrush: Update APCB file ...................................................................... mb/google/guybrush: Update APCB file The existing APCB file only has 4 SPD slots. This will not be enough for DeWatt devices due to upcoming changes in how RAM IDs are allocated for that variant. This commit updates the APCB file to have 16 slots which is sufficient for DeWatt. BUG=b:224884904 TEST=Used apcb_v3_edit to verify that the APCB file has 16 slots, checked that AP firmware images built with this file boot correctly Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318 --- M mainboard/google/guybrush/APCB_CZN_D4.bin M mainboard/google/guybrush/Release.txt 2 files changed, 11 insertions(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Martin L Roth: Verified; Looks good to me, approved diff --git a/mainboard/google/guybrush/APCB_CZN_D4.bin b/mainboard/google/guybrush/APCB_CZN_D4.bin index ff99c5d..7fe382e 100644 --- a/mainboard/google/guybrush/APCB_CZN_D4.bin +++ b/mainboard/google/guybrush/APCB_CZN_D4.bin Binary files differ diff --git a/mainboard/google/guybrush/Release.txt b/mainboard/google/guybrush/Release.txt index df803b8..7b4aa6b 100644 --- a/mainboard/google/guybrush/Release.txt +++ b/mainboard/google/guybrush/Release.txt @@ -4,6 +4,17 @@ Files: APCB_CZN_D4.bin - Data only - No license, ABI or Version # +2022-03-21: +- Increase the number of SPD slots in APCB_CZN_D4.bin from 4 to 16 + Slots 0 - 3: + lp4x-spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A + lp4x-spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F + lp4x-spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 + lp4x-spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B + + Slots 4 - 15: + Place holder SPDs from Majolica + 2021-04-05: - Fix UMAmode - Enable VBL/PSP to control eDP VDD. -- To view, visit https://review.coreboot.org/c/blobs/+/62963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: blobs Gerrit-Branch: master Gerrit-Change-Id: Ifbfe2c61c42cd503a70fd84c51ce184c40fed318 Gerrit-Change-Number: 62963 Gerrit-PatchSet: 5 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63010 ) Change subject: include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION ...................................................................... include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION This patch resolves compilation issue of including `efi_datatype.h` in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h` hence, included to resolve compilation issue. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd --- M src/include/efi/efi_datatype.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/63010/1 diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 7eefad3..5415ae8 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -8,6 +8,7 @@ #if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION #include <Pi/PiPeiCis.h> +#include <Protocol/MpService.h> /* Data structure for EFI_PEI_SERVICE. */ typedef EFI_PEI_SERVICES efi_pei_services; -- To view, visit https://review.coreboot.org/c/coreboot/+/63010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Gerrit-Change-Number: 63010 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Tim Wawrzynczak. Hello Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63008 to look at the new patch set (#2). Change subject: soc/intel/alderlake: Use coreboot native event handler for FSP-M/S ...................................................................... soc/intel/alderlake: Use coreboot native event handler for FSP-M/S This patch assigns FSP handler event for FSP-M and FSP-S with coreboot romstage and ramstage debug handler when FSP_DEBUG_EVENT_HANDLER_IN_COREBOOT Kconfig is enabled. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I665def977faaae45f6f834d75e8456859093ba49 --- M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/63008/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63008 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I665def977faaae45f6f834d75e8456859093ba49 Gerrit-Change-Number: 63008 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
by Subrata Banik (Code Review) 22 Mar '22

22 Mar '22

Attention is currently required from: Andrey Petrov. Hello Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63007 to look at the new patch set (#2). Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler ...................................................................... drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler This patch implements coreboot native debug handler to manage the FSP event messages. `FSP Event Handlers` feature introduced in FSP to generate event messages to aid in the debugging of firmware issues. This eliminates the need for FSP to directly write debug messages to the UART and FSP might not need to know the board related UART port configuration. Instead FSP signals the bootloader to inform it of a new debug message. This allows the coreboot to provide board specific methods of reporting debug messages, example: legacy UART or LPSS UART etc. This implementation has several advantages as: 1. FSP relies on XIP `DebugLib` driver even while printing FSP-S debug messages, hence, without ROM being cached, post `romstage` would results into sluggish boot with FSP debug enabled. This patch utilities coreboot native debug implementation which is XIP during FSP-M and relocatable to DRAM based resource for FSP-S. 2. This patch simplifies the FSP DebugLib implementation and remove the need to have serialport library. Instead coreboot `printk` can be used for display FSP serial messages. Additionally, unifies the debug library between coreboot and FSP. 3. This patch is also useful to get debug prints even with FSP non-serial image (refer to `Note` below) as FSP PEIMs are now leveraging coreboot debug library instead FSP `NULL` DebugLib reference for release build. 4. Can optimize the FSP binary size by removing the DebugLib dependency from most of FSP PEIMs, for example: on Alder Lake FSP-M debug binary size is reduced by ~100KB+ and FSP-S debug library size is also reduced by ~300KB+ (FSP-S debug and release binary size is exactly same with this code changes). The total savings is ~400KB for each FSP copy, and in case of Chrome AP firmware with 3 copies, the total savings would be 400KB * 3 = ~1.2MB. Note: Need to modify FSP source code to remove `MDEPKG_NDEBUG` as compilation flag for release build and generate FSP binary with non-NULL FSP debug wrapper module injected (to allow FSP event handler to execute even with FSP non-serial image) in the final FSP.fd. BUG=b:225544587 TEST=Able to build and boot brya. Also, verified the FSP debug log is exactly same before and with this code change. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fsp_debug_event.c A src/drivers/intel/fsp2_0/include/fsp/fsp_debug_event.h 4 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/63007/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63007 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1018e67d70492b18c76531f9e78d3b58fa435cd4 Gerrit-Change-Number: 63007 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022