coreboot-gerrit March 2022

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Change in coreboot[master]: mb/dell: Convert OptiPlex 9010 into directory with variants
by Krystian Hebel (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Michał Żygowski. Krystian Hebel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62211 ) Change subject: mb/dell: Convert OptiPlex 9010 into directory with variants ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4075f0ae3b24892fcc2be07061a01f8070659239 Gerrit-Change-Number: 62211 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 12:55:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/cherry: Add MAX98390 support for DOJO
by Hung-Te Lin (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Rex-BC Chen, Yu-Ping Wu. Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63083 ) Change subject: mb/google/cherry: Add MAX98390 support for DOJO ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/cherry/Kconfig: https://review.coreboot.org/c/coreboot/+/63083/comment/5aa88879_9c0c9be9 PS2, Line 66: BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_TOMATO what about if !BOARD_GOOGLE_DOJO In fact I wonder if we can say default y if !CHERRY_USE_RT1011 && !CHERRY_USE_MAX98380 -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 12:11:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Paul Menzel, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63025 ) Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > would be good if you can create patches to do this in picasso and sabrina too Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 3 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 24 Mar 2022 11:46:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held. Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63088 ) Change subject: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/sabrina/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/63088/1 diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index c355a70..9893a8b 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -13,6 +13,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -39,7 +40,10 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Gerrit-Change-Number: 63088 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume
by Fred Reitberger (Code Review) 24 Mar '22

24 Mar '22

Fred Reitberger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63087 ) Change subject: soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/picasso/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/63087/1 diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index de6e9c0..f14ee49 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,6 +10,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -41,7 +42,10 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Gerrit-Change-Number: 63087 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: HACK trogdor: optimize coreboot.rom for T32 flash script HACK
by build bot (Jenkins) (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Ravi Kumar Bokka, Shelley Chen, Sudheer Amrabadi, Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36278 ) Change subject: HACK trogdor: optimize coreboot.rom for T32 flash script HACK ...................................................................... Patch Set 256: Verified-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/36278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5293ac9365bf4ac74bc475e70a02062f5371f9b8 Gerrit-Change-Number: 36278 Gerrit-PatchSet: 256 Gerrit-Owner: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 11:43:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sc7280: Add PCIe host controller driver
by build bot (Jenkins) (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Ravi Kumar Bokka, Furquan Shaikh, Paul Menzel, Julius Werner, Prasad Malisetty, mturney mturney. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/53902 ) Change subject: sc7280: Add PCIe host controller driver ...................................................................... Patch Set 75: Verified+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/53902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccf60aa56541f5230fa9c3f821d7709615c36631 Gerrit-Change-Number: 53902 Gerrit-PatchSet: 75 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Comment-Date: Thu, 24 Mar 2022 11:40:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Adjust FMD file to chromeos.fmd for kano
by David Wu (Code Review) 24 Mar '22

24 Mar '22

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63086 ) Change subject: mb/google/brya: Adjust FMD file to chromeos.fmd for kano ...................................................................... mb/google/brya: Adjust FMD file to chromeos.fmd for kano This patch adjusts FMD file to chromeos.fmd for kano BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63086/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 199db11..3d47ab3 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -122,7 +122,7 @@ default 0x50 config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" -- To view, visit https://review.coreboot.org/c/coreboot/+/63086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Gerrit-Change-Number: 63086 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Performance improvement by removing delays in cpucp init
by Ravi Kumar Bokka (Code Review) 24 Mar '22

24 Mar '22

Ravi Kumar Bokka has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63085 ) Change subject: Performance improvement by removing delays in cpucp init ...................................................................... Performance improvement by removing delays in cpucp init As cpucp prepare takes 300 msec moving to before ramstage BUG=b:218406702 TEST=Validated on qualcomm sc7280 development board Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad(a)quicinc.com> --- M src/mainboard/google/herobrine/romstage.c M src/soc/qualcomm/sc7280/cpucp_load_reset.c 2 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63085/1 diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c index 2ea78b8..3dcb167 100644 --- a/src/mainboard/google/herobrine/romstage.c +++ b/src/mainboard/google/herobrine/romstage.c @@ -5,6 +5,7 @@ #include <soc/qclib_common.h> #include "board.h" #include <soc/shrm.h> +#include <soc/cpucp.h> static void prepare_usb(void) { @@ -15,11 +16,21 @@ reset_usb0(); } +void cpucp_prepare(void) +{ + /* allow NS access to EPSS memory*/ + setbits32(&epss_top->access_override, 0x1); + + /* Enable subsystem clock. Required for CPUCP PDMEM access*/ + setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); +} + void platform_romstage_main(void) { shrm_fw_load_reset(); /* QCLib: DDR init & train */ qclib_load_and_run(); + cpucp_prepare(); prepare_usb(); /* This rail needs to be stable by the time we take the FPMCU out of reset in ramstage, so already turn it on here. This needs to happen diff --git a/src/soc/qualcomm/sc7280/cpucp_load_reset.c b/src/soc/qualcomm/sc7280/cpucp_load_reset.c index d754531..b95cc75 100644 --- a/src/soc/qualcomm/sc7280/cpucp_load_reset.c +++ b/src/soc/qualcomm/sc7280/cpucp_load_reset.c @@ -9,24 +9,13 @@ #include <device/mmio.h> #include <timer.h> -void cpucp_prepare(void) -{ - /* allow NS access to EPSS memory*/ - setbits32(&epss_top->access_override, 0x1); - /* Enable subsystem clock. Required for CPUCP PDMEM access*/ - setbits32(&epss_fast->epss_muc_clk_ctrl, 0x1); - if (!wait_ms(300, ((read32(&epss_fast->epss_muc_clk_ctrl) & 0x1) != 0x1))) - printk(BIOS_ERR, "%s: cannot get CPUCP PDMEM access.\n", __func__); -} void cpucp_fw_load_reset(void) { struct prog cpucp_fw_prog = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/cpucp"); - cpucp_prepare(); - if (!selfload(&cpucp_fw_prog)) die("SOC image: CPUCP load failed"); -- To view, visit https://review.coreboot.org/c/coreboot/+/63085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb Gerrit-Change-Number: 63085 Gerrit-PatchSet: 1 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Add support for PCI MMIO CONFIG access.
by Ravi Kumar Bokka (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Ravi Kumar Bokka, Furquan Shaikh, Arthur Heymans, Prasad Malisetty. Hello build bot (Jenkins), Furquan Shaikh, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57615 to look at the new patch set (#40). Change subject: libpayload: Add support for PCI MMIO CONFIG access. ...................................................................... libpayload: Add support for PCI MMIO CONFIG access. Add MMIO method to access PCIe config space from payloads. Defined read/write config 8/16/32 functions for ARM arch in libpayload pci driver. In pci driver, PCIe MMIO config base info extracts through coreboot tables and initializes the ATU for every read/write config access. BUG=b:182963902,b:216686574,b:181098581 TEST=Validated on qualcomm sc7280 development board Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Signed-off-by: Prasad Malisetty <quic_pmaliset(a)quicinc.com> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.herobrine M payloads/libpayload/drivers/Makefile.inc R payloads/libpayload/drivers/pci_io_ops.c C payloads/libpayload/drivers/pci_mmio_ops.c A payloads/libpayload/drivers/qc_pci_mmio_ops.c M payloads/libpayload/include/pci.h A payloads/libpayload/include/qc_pci.h 8 files changed, 250 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/57615/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/57615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d1217502cbd7d4d0cdd298919ae82435630d61c Gerrit-Change-Number: 57615 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022