coreboot-gerrit March 2022

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Change in coreboot[master]: libpayload: Export PCIe config info from coreboot to libpayload
by Ravi Kumar Bokka (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Ravi Kumar Bokka, mturney mturney, Furquan Shaikh, Kyösti Mälkki, Prasad Malisetty. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Furquan Shaikh, Arthur Heymans, Kyösti Mälkki, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/57614 to look at the new patch set (#40). Change subject: libpayload: Export PCIe config info from coreboot to libpayload ...................................................................... libpayload: Export PCIe config info from coreboot to libpayload Export PCIe config base info to payloads through coreboot tables. Fill PCIe config base, ATU address and config size in cbmem entry. BUG=b:182963902,b:216686574,b:181098581 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Prasad Malisetty <quic_pmaliset(a)quicinc.com> Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940 --- M payloads/libpayload/include/sysinfo.h M payloads/libpayload/libc/coreboot.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/commonlib/include/commonlib/coreboot_tables.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c 6 files changed, 36 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/57614/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/57614 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ca2be55b98c8d1b86576072078cdda02ac55940 Gerrit-Change-Number: 57614 Gerrit-PatchSet: 40 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Prasad Malisetty <pmaliset(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/qualcomm/common: verify size of memchipinfo structure
by Ravi Kumar Bokka (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Ravi Kumar Bokka. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63026 to look at the new patch set (#2). Change subject: soc/qualcomm/common: verify size of memchipinfo structure ...................................................................... soc/qualcomm/common: verify size of memchipinfo structure BUG=b:182963902,b:177917361 TEST=Validated on qualcomm sc7280 development board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h M src/soc/qualcomm/common/qclib.c 2 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/63026/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d59669adaf287d0eb7b58ccb0fe3f98e3d23281 Gerrit-Change-Number: 63026 Gerrit-PatchSet: 2 Gerrit-Owner: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Paul Menzel, Nick Vaccaro, Eric Lai, Andrey Petrov. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62942 ) Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62942/comment/4486d8e4_92326ea5 PS2, Line 9: This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp : from FPDT (Firmware Performance Data Table) and display as part of : ramstage boot stage if the SoC user selects the required : `GET_FSP_TIMESTAMP` config. > > Extracting this data sounds great. But instead of printing it to the CBMEM console, could you please add them to the CBMEM timestamp table? > > we already have FSP TS data as part of cbmem -t table. what this CL does is to have detailed break down of the FSP timestamp which might be useful to debug or optimise the FSP per component boot time. > > > > > Is the FSP data theoretically also accessible from the operating sytsem? > > Not sure, if I understood your comments, but cbmem -t is able to show the FSP API wise boot time impact. where this CL is more deep dive into those FSP APIs. > > 950:calling FspMemoryInit 1,936,192 (59,275) > 951:returning from FspMemoryInit 81,024,105 (79,087,913) > 971:loading FSP-S 82,941,127 (21,318) > 954:calling FspSiliconInit 83,166,997 (219,188) > 955:returning from FspSiliconInit 102,564,474 (19,397,476) > 962:calling FspMultiPhaseSiInit 102,564,627 (152) > 963:returning from FspMultiPhaseSiInit 108,645,466 (6,080,839) @Paul, any further opens ? File src/drivers/intel/fsp2_0/fsp_timestamp.c: https://review.coreboot.org/c/coreboot/+/62942/comment/8670e100_77f80b18 PS4, Line 111: : BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_get_timestamp, NULL); : BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_get_timestamp, NULL); > Instead of boot state entries, can we just add call fsp_print_timestamps() from somewhere in the flo […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 10:48:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data
by Subrata Banik (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Paul Menzel, Nick Vaccaro, Eric Lai, Andrey Petrov. Hello build bot (Jenkins), Kangheui Won, Maulik V Vaghela, Tim Wawrzynczak, Nick Vaccaro, Eric Lai, Andrey Petrov, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62942 to look at the new patch set (#5). Change subject: drivers/intel/fsp2_0: Add provision to extract FSP Performance Data ...................................................................... drivers/intel/fsp2_0: Add provision to extract FSP Performance Data This patch enriches coreboot FSP2.0 driver to extract the FSP timestamp from FPDT (Firmware Performance Data Table) and display right after FSP-S exits (from `fsp_silicon_init()` function), based on SoC user selects the required `GET_FSP_TIMESTAMP` config. The prerequisite to this implementation is to have FSP binary built with `PcdFspPerformanceEnable` PCD set to `TRUE` to allow FSP to populate the FPDT HOB. BUG=b:216635831 TEST=Able to dump FSP performance data with GET_FSP_TIMESTAMP Kconfig selected and met the FSP prerequisites. +--------------------------------------------------+ |------ FSP Performance Timestamp Table Dump ------| +--------------------------------------------------+ |Perf-ID Timestamp(ms) String/GUID | +--------------------------------------------------+ 0 460253 SEC/52c05b14-0b98-496c-bc3b04b50211d680 50 460263 PEI/52c05b14-0b98-496c-bc3b04b50211d680 40 460274 PreMem/52c05b14-0b98-496c-bc3b04b50211d680 1 495803 9b3ada4f-ae56-4c24-8deaf03b7558ae50 2 508959 9b3ada4f-ae56-4c24-8deaf03b7558ae50 1 515253 6141e486-7543-4f1a-a579ff532ed78e75 2 525453 6141e486-7543-4f1a-a579ff532ed78e75 1 532059 baeb5bee-5b33-480a-8ab7b29c85e7ceab 2 546806 baeb5bee-5b33-480a-8ab7b29c85e7ceab 1 553302 1b04374d-fa9c-420f-ac62fee6d45e8443 2 563859 1b04374d-fa9c-420f-ac62fee6d45e8443 1 569955 88c17e54-ebfe-4531-a992581029f58126 2 575753 88c17e54-ebfe-4531-a992581029f58126 1 582099 a8499e65-a6f6-48b0-96db45c266030d83 50f0 599599 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 50f1 716649 unknown name/3112356f-cc77-4e82-86d53e25ee8192a4 2 728507 a8499e65-a6f6-48b0-96db45c266030d83 1 734755 9e1cc850-6731-4848-87526673c7005eee .... Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.inc A src/drivers/intel/fsp2_0/fsp_timestamp.c M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/silicon_init.c 5 files changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/62942/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/62942 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1b7f6b98bafeec0afe843f0f78c99c2f34f50b3 Gerrit-Change-Number: 62942 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]abuild: Build with clang only when supported
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63084 to review the following change. Change subject: [WIP]abuild: Build with clang only when supported ...................................................................... [WIP]abuild: Build with clang only when supported Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/abuild/abuild 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63084/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index cc149a8..2585b57 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -456,6 +456,14 @@ local FORCE_ENABLED_CROS=0 fi + if [ "$clang" = true ]; then + check_config "$build_dir" "clang" "CONFIG_COMPILER_LLVM_CLANG=y" + if [ $? -ne 0 ]; then + echo "${MAINBOARD} doesn't support Clang, skipping." + return + fi + fi + if [ $BUILDENV_CREATED -ne 0 ] || [ $MAINBOARD_OK -ne 0 ] || [ $VENDOR_OK -ne 0 ] || [ $FORCE_ENABLED_CROS -eq 1 ]; then junit " <testcase classname='board${testclass/#/.}' name='$BUILD_NAME' >" @@ -587,7 +595,7 @@ [-J|--junit] Write JUnit formatted xml log file [-K|--kconfig <name>] Prepend file to generated Kconfig [-l|--loglevel <num>] Set loglevel - [-L|--clang] Use clang + [-L|--clang] Use clang on supported arch [-o|--outdir <path>] Store build results in path (defaults to $TARGET) [-p|--payloads <dir>] Use payloads in <dir> to build images @@ -671,6 +679,7 @@ fi chromeos=false +clang=false clean_work=false clean_objs=false verboseopt='V=0' @@ -738,6 +747,7 @@ configoptions="${configoptions}CONFIG_ANY_TOOLCHAIN=y\n" ;; -L|--clang) shift + clang=true customizing="${customizing}, clang" configoptions="${configoptions}CONFIG_COMPILER_LLVM_CLANG=y\n# CONFIG_COMPILER_GCC is not set\n" ;; -- To view, visit https://review.coreboot.org/c/coreboot/+/63084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I362fcd0f795d27f13dde793a79774f08c497bd38 Gerrit-Change-Number: 63084 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/cherry: Add MAX98390 support for DOJO
by Rex-BC Chen (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Hung-Te Lin. Hello Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63083 to look at the new patch set (#2). Change subject: mb/google/cherry: Add MAX98390 support for DOJO ...................................................................... mb/google/cherry: Add MAX98390 support for DOJO In DOJO, we use MAX98390 to output audio. Therefore, we add a config "CHERRY_USE_MAX98390" to enable it. BUG=b:204391159 BRANCH=cherry TEST=emerge-cherry coreboot TEST=Verify beep function through CLI in depthcharge successfully Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/pll.c 5 files changed, 50 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63083/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: drivers/intel/dptf: Add support for Power participant
by Varshit B Pandya (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Lance Zhao, Subrata Banik, Tim Wawrzynczak, Rizwan Qureshi. Varshit B Pandya has removed Felix Held from this change. ( https://review.coreboot.org/c/coreboot/+/62944 ) Change subject: drivers/intel/dptf: Add support for Power participant ...................................................................... Removed cc Felix Held. -- To view, visit https://review.coreboot.org/c/coreboot/+/62944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I437e509f58df1777d75e5981f0a5a63095ccb6a3 Gerrit-Change-Number: 62944 Gerrit-PatchSet: 3 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: deleteReviewer

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Change in coreboot[master]: mb/google/cherry: Add MAX98390 support for DOJO
by Rex-BC Chen (Code Review) 24 Mar '22

24 Mar '22

Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63083 ) Change subject: mb/google/cherry: Add MAX98390 support for DOJO ...................................................................... mb/google/cherry: Add MAX98390 support for DOJO In DOJO, we use MAX98390 to output audio. Therefore, we add a config "CHERRY_USE_MAX98390" to enable it. BUG=b:204391159 BRANCH=none TEST=emerge-cherry coreboot Signed-off-by: Trevor Wu <trevor.wu(a)mediatek.com> Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 --- M src/mainboard/google/cherry/Kconfig M src/mainboard/google/cherry/chromeos.c M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/mt8195/include/soc/addressmap.h M src/soc/mediatek/mt8195/pll.c 5 files changed, 50 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63083/1 diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig index e45b259..8199eb4 100644 --- a/src/mainboard/google/cherry/Kconfig +++ b/src/mainboard/google/cherry/Kconfig @@ -63,5 +63,11 @@ config CHERRY_USE_RT1019 bool - default y + default y if BOARD_GOOGLE_CHERRY || BOARD_GOOGLE_TOMATO + default n + +config CHERRY_USE_MAX98390 + bool + default y if BOARD_GOOGLE_DOJO + default n endif diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c index 13b673c..4be6b75 100644 --- a/src/mainboard/google/cherry/chromeos.c +++ b/src/mainboard/google/cherry/chromeos.c @@ -47,12 +47,18 @@ {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, }; + struct lb_gpio spk_gpios[] = { + {GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"}, + }; + lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); if (CONFIG(CHERRY_USE_RT1019)) lb_add_gpios(gpios, rt1019_gpios, ARRAY_SIZE(rt1019_gpios)); else if (CONFIG(CHERRY_USE_RT1011)) lb_add_gpios(gpios, rt1011_gpios, ARRAY_SIZE(rt1011_gpios)); + else + lb_add_gpios(gpios, spk_gpios, ARRAY_SIZE(spk_gpios)); } int tis_plat_irq_status(void) diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index 92d8ee1..3fb599b 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -92,6 +92,27 @@ return true; } +static void configure_i2s(void) +{ + /* Audio PWR */ + mtcmos_audio_power_on(); + mtcmos_protect_audio_bus(); + + /* SoC I2S */ + gpio_set_mode(GPIO(GPIO_02), PAD_GPIO_02_FUNC_TDMIN_LRCK); + gpio_set_mode(GPIO(GPIO_03), PAD_GPIO_03_FUNC_TDMIN_BCK); + gpio_set_mode(GPIO(I2SO2_D0), PAD_I2SO2_D0_FUNC_I2SO2_D0); +} + +static void configure_audio(void) +{ + if (CONFIG(CHERRY_USE_RT1011) || CONFIG(CHERRY_USE_MAX98390)) + mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST); + + if (CONFIG(CHERRY_USE_MAX98390)) + configure_i2s(); +} + static void mainboard_init(struct device *dev) { if (display_init_required()) @@ -103,9 +124,7 @@ mtk_msdc_configure_sdcard(); setup_usb_host(); - /* for audio usage */ - if (CONFIG(CHERRY_USE_RT1011)) - mtk_i2c_bus_init(I2C2, I2C_SPEED_FAST); + configure_audio(); if (dpm_init()) printk(BIOS_ERR, "dpm init failed, DVFS may not work\n"); diff --git a/src/soc/mediatek/mt8195/include/soc/addressmap.h b/src/soc/mediatek/mt8195/include/soc/addressmap.h index f2714da..a5c4b0d 100644 --- a/src/soc/mediatek/mt8195/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8195/include/soc/addressmap.h @@ -49,6 +49,7 @@ SSPM_SRAM_BASE = IO_PHYS + 0x00400000, SSPM_CFG_BASE = IO_PHYS + 0x00440000, SCP_CFG_BASE = IO_PHYS + 0x00700000, + SCP_ADSP_CFG_BASE = IO_PHYS + 0x00720000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, diff --git a/src/soc/mediatek/mt8195/pll.c b/src/soc/mediatek/mt8195/pll.c index df4ae30..046008c 100644 --- a/src/soc/mediatek/mt8195/pll.c +++ b/src/soc/mediatek/mt8195/pll.c @@ -28,6 +28,14 @@ check_member(mt8195_pericfg_ao_regs, peri_module_sw_cg_0_set, 0x0010); static struct mt8195_pericfg_ao_regs *const mt8195_pericfg_ao = (void *)PERICFG_AO_BASE; +struct mt8195_scp_adsp_regs { + u32 reserved1[96]; + u32 audiodsp_ck_cg; /* 0x180 */ +}; +check_member(mt8195_scp_adsp_regs, audiodsp_ck_cg, 0x0180); +static struct mt8195_scp_adsp_regs *const mt8195_scp_adsp = + (void *)SCP_ADSP_CFG_BASE; + enum mux_id { TOP_AXI_SEL, TOP_SPM_SEL, @@ -760,6 +768,12 @@ /* turn off unused clock */ write32(&mt8195_pericfg_ao->peri_module_sw_cg_0_set, 0x10); + + /* scp_dsp for audio */ + clrbits32(&mt8195_scp_adsp->audiodsp_ck_cg, BIT(0)); + + /* audio 26M */ + setbits32(&mt8195_infracfg_ao->module_sw_cg_2_clr, BIT(4)); } void mt_pll_raise_little_cpu_freq(u32 freq) -- To view, visit https://review.coreboot.org/c/coreboot/+/63083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b6bc5a5520292dd502b0389217f5062479b4490 Gerrit-Change-Number: 63083 Gerrit-PatchSet: 1 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] mb/google/dedede: Update DRAM population
by Teddy Shih (Code Review) 24 Mar '22

24 Mar '22

Teddy Shih has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/62556 ) Change subject: [TEST] mb/google/dedede: Update DRAM population ...................................................................... Abandoned For test only -- To view, visit https://review.coreboot.org/c/coreboot/+/62556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d Gerrit-Change-Number: 62556 Gerrit-PatchSet: 3 Gerrit-Owner: Teddy Shih <teddyshih(a)ami.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in coreboot[master]: Kconfig: Mark clang as ready to use on some arch
by Arthur Heymans (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63081 ) Change subject: Kconfig: Mark clang as ready to use on some arch ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: Abuild would just build with gcc here... -- To view, visit https://review.coreboot.org/c/coreboot/+/63081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f1bad59bda94f60f4a141237ede11f6eb93cc2 Gerrit-Change-Number: 63081 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 09:52:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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