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Hello Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62173
to look at the new patch set (#9).
Change subject: util/testing: Buildtest with clang
......................................................................
util/testing: Buildtest with clang
Some platforms correctly build and boot with clang.
Add this to our CI.
Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/testing/Makefile.inc
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/62173/9
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Gerrit-Change-Number: 62173
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Change subject: images: Add coreboot_hare.svg
......................................................................
Abandoned
Upstream didn't want bootlogo in the end
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
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to review the following change.
Change subject: [TESTONLY]Kconfig: Build all board with clang
......................................................................
[TESTONLY]Kconfig: Build all board with clang
See what the fallout is.
Change-Id: Ia35f9cfb16ddc6a248baf2ee6aa864a3ac4e9b41
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/63082/1
diff --git a/src/Kconfig b/src/Kconfig
index 743440d..6674d9a 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -84,6 +84,7 @@
config ARCH_SUPPORTS_CLANG
bool
+ default y
help
Opt-in flag for architectures that generally work well with CLANG.
By default the option would be hidden.
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Hello Arthur Heymans,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63081
to review the following change.
Change subject: Kconfig: Mark clang as ready to use on some arch
......................................................................
Kconfig: Mark clang as ready to use on some arch
This adds 2 flags:
* invisible opt-in flag for platforms on which clang seems to work
* visible opt-in flag to allow experimenting
Clang seems to work rather well on x86_32 so it makes sense to start
adding that to Jenkins buildtesting, which this allows.
Change-Id: I46f1bad59bda94f60f4a141237ede11f6eb93cc2
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/Kconfig
M src/arch/x86/Kconfig
2 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/63081/1
diff --git a/src/Kconfig b/src/Kconfig
index 3811efc..743440d 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -70,19 +70,30 @@
For details see http://gcc.gnu.org.
config COMPILER_LLVM_CLANG
- bool "LLVM/clang (TESTING ONLY - Not currently working)"
+ bool "LLVM/clang"
+ depends on ALLOW_EXPERIMENTAL_CLANG || ARCH_SUPPORTS_CLANG
help
Use LLVM/clang to build coreboot. To use this, you must build the
coreboot version of the clang compiler. Run the command
make clang
- Note that this option is not currently working correctly and should
- really only be selected if you're trying to work on getting clang
- operational.
+ Note that Clang is not currently working on all architectures.
For details see http://clang.llvm.org.
endchoice
+config ARCH_SUPPORTS_CLANG
+ bool
+ help
+ Opt-in flag for architectures that generally work well with CLANG.
+ By default the option would be hidden.
+
+config ALLOW_EXPERIMENTAL_CLANG
+ bool "Allow experimental LLVM/Clang"
+ help
+ On some architectures CLANG does not work that well.
+ Use this only to try to get CLANG working.
+
config ANY_TOOLCHAIN
bool "Allow building with any toolchain"
default n
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 4052b2e..11be921 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -33,6 +33,7 @@
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
+ select ARCH_SUPPORTS_CLANG
# stage selectors for x64
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Hello Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62173
to look at the new patch set (#8).
Change subject: util/testing: Buildtest with clang
......................................................................
util/testing: Buildtest with clang
Some platforms correctly build and boot with clang.
Add this to our CI.
Change-Id: I82d756e071a0e575db73fbd91167d27cae3ddc18
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/testing/Makefile.inc
1 file changed, 2 insertions(+), 0 deletions(-)
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I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/63080
to look at the new patch set (#4).
Change subject: mb/google/brask/variants/moli: update overridetree for moli
......................................................................
mb/google/brask/variants/moli: update overridetree for moli
Add FW_CONFIG STORAGE for moli overridetree.cb.
BUG=b:220814038
TEST=emerge-brask coreboot.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
---
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/brask/variants/moli: update overridetree for moli
......................................................................
mb/google/brask/variants/moli: update overridetree for moli
Add FW_CONFIG STORAGE for moli overridetree.cb.
BUG=b:220814038
TEST=emerge-brask chromeos-ec coreboot depthcharge vboot_reference libpayload chromeos-bootimage coreboot-private-files intel-adlfsp coreboot-private-files-baseboard-brya.
Signed-off-by: Raihow Shi <raihow_shi(a)wistron.corp-partner.google.com>
Change-Id: If83031edcd90ea746704590765102b9b0dee03c1
---
M src/mainboard/google/brya/variants/moli/overridetree.cb
1 file changed, 4 insertions(+), 0 deletions(-)
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Change subject: mb/google/brask/variants/moli: update overridetree for moli
......................................................................
Patch Set 2:
This change is ready for review.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63007 )
Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> > > Fun fact: the USF spec thinks this a bad idea: https://universalscalablefirmware.github.io/documentation/6_debug.html#trac…. It says the Soc Abstraction Layer (basically FSP) should be in charge of selecting where console gets outputted.
> >
> > I guess the term BIOS being used their is misleading, because the definition on BIOS is now evolved over time and unless specified some thing like silicon ref aka FSP or platform code aka coreboot, this is not clear when someone says "BIOS shall support sending trace messages to all BIOS accessible HW interfaces on the platform.'
> >
> > I can replace BIOS with coreboot here for my easy understanding and say "yes, coreboot would like to support sending traces to coreboot accessible HW interface for the platform."
>
> Ok that would make sense, however "BIOS modules don’t control which trace output is used. SAL layer shall implement a middleware trace class which routes the messages to enabled interfaces such as NPK or UART." seems to indicate otherwise? Anyway no point in discussing things when terminology isn't clear to either of us.
:) sure Arthur. "SAL is new baby which has soul of an old person", you are right, we can avoid having that discussion.
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Change subject: drivers/intel/fsp2_0: Add native implementation for FSP Debug Handler
......................................................................
Patch Set 3: Code-Review+2
(1 comment)
Patchset:
PS2:
> > Fun fact: the USF spec thinks this a bad idea: https://universalscalablefirmware.github.io/documentation/6_debug.html#trac…. It says the Soc Abstraction Layer (basically FSP) should be in charge of selecting where console gets outputted.
>
> I guess the term BIOS being used their is misleading, because the definition on BIOS is now evolved over time and unless specified some thing like silicon ref aka FSP or platform code aka coreboot, this is not clear when someone says "BIOS shall support sending trace messages to all BIOS accessible HW interfaces on the platform.'
>
> I can replace BIOS with coreboot here for my easy understanding and say "yes, coreboot would like to support sending traces to coreboot accessible HW interface for the platform."
Ok that would make sense, however "BIOS modules don’t control which trace output is used. SAL layer shall implement a middleware trace class which routes the messages to enabled interfaces such as NPK or UART." seems to indicate otherwise? Anyway no point in discussing things when terminology isn't clear to either of us.
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