coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/*/meminit.c: Fix formatted print
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63052 ) Change subject: soc/intel/*/meminit.c: Fix formatted print ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Gerrit-Change-Number: 63052 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:29:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/fam*/northbridge.c: Remove unused reset_memhole variable
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63042 ) Change subject: amd/fam*/northbridge.c: Remove unused reset_memhole variable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63042 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9231e0399d0b3ac6a608282571fc6d4aefad9dfb Gerrit-Change-Number: 63042 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:26:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: amd/fam*/northbridge.c: Fix unused hest variable
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63041 ) Change subject: amd/fam*/northbridge.c: Fix unused hest variable ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9104e4736a3c30b7592bb0e79a8ddc6af579800 Gerrit-Change-Number: 63041 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:25:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/amd/agesa: Add CFLAGS required by CLANG
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63040 ) Change subject: vendorcode/amd/agesa: Add CFLAGS required by CLANG ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Gerrit-Change-Number: 63040 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:23:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans, Angel Pons. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63024 ) Change subject: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/southbridge/intel/i82801jx/chip.h: https://review.coreboot.org/c/coreboot/+/63024/comment/5e151032_b8ce6275 PS2, Line 48: c5_enable [Out of topic] looks like that c5_enable is always set to 1 (same for c6_enable).... so why we rewrite 1 here "src/mainboard/lenovo/t400/devicetree.cb" ? -- To view, visit https://review.coreboot.org/c/coreboot/+/63024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379 Gerrit-Change-Number: 63024 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:18:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45/pm.c: Make clang happy
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans, Patrick Rudolph. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62172 ) Change subject: nb/intel/gm45/pm.c: Make clang happy ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Gerrit-Change-Number: 62172 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 24 Mar 2022 19:09:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values
by Elyes Haouas (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans. Hello build bot (Jenkins), Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62647 to look at the new patch set (#2). Change subject: include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values ...................................................................... include/spd.h: Fix DDR4_SPD_72B_SO_{R,U}DIMM values Regarding JEDEC Standard No. 21-C, Release 30, page 13, DDR4_SPD_72B_SO_RDIMM and DDR4_SPD_72B_SO_UDIMM values are respectively 0x08 and 0x09. Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb --- M src/include/spd.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/62647/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62647 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4e9c3814e2e7f379917bf93f7975af3aad31dbb Gerrit-Change-Number: 62647 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add APIs to check CSE's write protection info
by Felix Held (Code Review) 24 Mar '22

24 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62986 ) Change subject: soc/intel/common: Add APIs to check CSE's write protection info ...................................................................... soc/intel/common: Add APIs to check CSE's write protection info The patch add APIs to check CSE Region's write protection information. Also, adds helper functions to get the SPI controller's MMIO address to access to BIOS_GPR0 register. The BIOS_GPR0 indicates write and read protection details. During the coreboot image build, write protection is enabled for CSE RO. It is enabled through a Intel MFIT XML configuration. TEST=Verify write protection information of CSE Region Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62986 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/spi.h M src/soc/intel/common/block/spi/spi.c 2 files changed, 92 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/spi.h b/src/soc/intel/common/block/include/intelblocks/spi.h index 38c9a57..4ab4105 100644 --- a/src/soc/intel/common/block/include/intelblocks/spi.h +++ b/src/soc/intel/common/block/include/intelblocks/spi.h @@ -3,6 +3,17 @@ #ifndef SOC_INTEL_COMMON_BLOCK_SPI_H #define SOC_INTEL_COMMON_BLOCK_SPI_H +#include <types.h> + +/* + * Check if write protection for CSE RO is enabled or not. + * Returns true if write protection for CSE RO is enabled, false otherwise. + */ +bool is_spi_wp_cse_ro_en(void); + +/* Gets CSE RO's write protected area's base address and limit */ +void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *limit); + /* * SoC overrides * diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 50e1bea..0716e1a 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -1,8 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#define __SIMPLE_DEVICE__ + #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <device/pci_ops.h> #include <device/spi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> @@ -20,6 +24,83 @@ const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); +#define MMIO_BIOS_GPR0 0x98 + +union spi_bios_gpr0 { + struct { + /* Specified write protection is enabled */ + /* + * This field corresponds to flash address bits 26:12 + * and specifies the lower limit of protected range. + */ + uint32_t protect_range_base:15; + + /* Specifies read protection is enabled */ + uint32_t read_protect_en:1; + + /* + * This field corresponds to flash address bits 26:12 + * and specifies the upper limit of the protected range + */ + uint32_t protect_range_limit:15; + + uint32_t write_protect_en:1; + } __packed fields; + + uint32_t data; +}; + +/* Read SPI BAR 0 from PCI configuration space */ +static uintptr_t get_spi_bar(pci_devfn_t dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + assert(bar != 0); + /* + * Bits 31-12 are the base address as per EDS for SPI, + * Don't care about 0-11 bit + */ + return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; +} + +static uint32_t spi_read_bar(pci_devfn_t dev, uint32_t offset) +{ + return read32p(get_spi_bar(dev) + offset); +} + +static uint32_t spi_read_bios_gpr0(void) +{ + return spi_read_bar(PCH_DEV_SPI, MMIO_BIOS_GPR0); +} + +static uint32_t spi_get_wp_cse_ro_start_offset(union spi_bios_gpr0 bios_gpr0) +{ + return bios_gpr0.fields.protect_range_base << 12; +} + +static uint32_t spi_get_wp_cse_ro_limit(union spi_bios_gpr0 bios_gpr0) +{ + return bios_gpr0.fields.protect_range_limit << 12 | 0xfff; +} + +bool is_spi_wp_cse_ro_en(void) +{ + union spi_bios_gpr0 bios_gpr0; + + bios_gpr0.data = spi_read_bios_gpr0(); + return !!bios_gpr0.fields.write_protect_en; +} + +void spi_get_wp_cse_ro_range(uint32_t *base, uint32_t *limit) +{ + union spi_bios_gpr0 bios_gpr0; + + bios_gpr0.data = spi_read_bios_gpr0(); + *base = spi_get_wp_cse_ro_start_offset(bios_gpr0); + *limit = spi_get_wp_cse_ro_limit(bios_gpr0); +} + static int spi_dev_to_bus(struct device *dev) { return spi_soc_devfn_to_bus(dev->path.pci.devfn); -- To view, visit https://review.coreboot.org/c/coreboot/+/62986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If1da0fc410a15996f2e139809f7652127ef8761b Gerrit-Change-Number: 62986 Gerrit-PatchSet: 5 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
by Anil Kumar K (Code Review) 24 Mar '22

24 Mar '22

Attention is currently required from: Arthur Heymans, Subrata Banik, Selma Bensaid, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph, Felix Held. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... Patch Set 44: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/59638/comment/436d854b_201592f0 PS44, Line 32: efi_physical_address > > Hi Felix. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 44 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 24 Mar 2022 17:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Update blobs submodule to upstream master
by Felix Held (Code Review) 24 Mar '22

24 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63027 ) Change subject: Update blobs submodule to upstream master ...................................................................... Update blobs submodule to upstream master Updating from commit id f14575c: 2022-02-14 21:14:23 +0800 - (mb/google/guybrush: Add SPL table) to commit id 8c580e5: 2022-03-21 16:05:58 -0600 - (mb/google/guybrush: Update APCB file) This brings in 3 new commits. Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: Iee7a8c550a69bc50b82850b9bfac1a8ca5229557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63027 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/blobs 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/3rdparty/blobs b/3rdparty/blobs index f14575c..8c580e5 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit f14575cb9924b051cedfb4c1f62e3640b25f9dbd +Subproject commit 8c580e55da92252fa665b5038b87100d0e076d23 -- To view, visit https://review.coreboot.org/c/coreboot/+/63027 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee7a8c550a69bc50b82850b9bfac1a8ca5229557 Gerrit-Change-Number: 63027 Gerrit-PatchSet: 3 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit March 2022