coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/dmi.c: Fix implicit enum typing
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63051 ) Change subject: soc/amd/dmi.c: Fix implicit enum typing ...................................................................... soc/amd/dmi.c: Fix implicit enum typing Clang complains about implicit enum typing so make it explicit. Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63051 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/common/fsp/dmi.c 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/fsp/dmi.c b/src/soc/amd/common/fsp/dmi.c index 64a5685..5596f97 100644 --- a/src/soc/amd/common/fsp/dmi.c +++ b/src/soc/amd/common/fsp/dmi.c @@ -52,8 +52,9 @@ dimm->rank_per_dimm = dmi17->Attributes; - dimm->mod_type = smbios_form_factor_to_spd_mod_type(dmi17->MemoryType, - dmi17->FormFactor); + dimm->mod_type = smbios_form_factor_to_spd_mod_type( + (smbios_memory_type)dmi17->MemoryType, + (smbios_memory_form_factor)dmi17->FormFactor); dimm->bus_width = smbios_bus_width_to_spd_width(dmi17->MemoryType, dmi17->TotalWidth, dmi17->DataWidth); -- To view, visit https://review.coreboot.org/c/coreboot/+/63051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20aba3bd3af8a7292e04d2496c3cba1ab6ba3019 Gerrit-Change-Number: 63051 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63121 ) Change subject: vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table ...................................................................... vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table Sabrina only supports PCIe and no SATA or 10 GBit/s ethernet on its DXIO lanes. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 --- M src/vendorcode/amd/fsp/sabrina/platform_descriptors.h 1 file changed, 7 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/63121/1 diff --git a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h index ada9bbd..cc6b78c 100644 --- a/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/sabrina/platform_descriptors.h @@ -160,29 +160,20 @@ } fsp_ddi_descriptor; /* - * Cezanne DXIO Descriptor: Used for assigning lanes to PCIe/SATA/XGBE engines, - * configure bifurcation and other settings. Beware that the lane numbers in - * here are the logical and not the physical lane numbers! + * Sabrina DXIO Descriptor: Used for assigning lanes to PCIe engines, configure + * bifurcation and other settings. Beware that the lane numbers in here are the + * logical and not the physical lane numbers! * - * Cezanne DXIO logical lane to physical PCIe lane mapping: + * Sabrina DXIO logical lane to physical PCIe lane mapping: * - * logical | FT6 | AM4 - * --------|------------|---------------------- - * [00:03] | GPP[00:03] | GPP[00:03] - * [04:07] | GPP[04:07] | GPP[04:07]/HUB[00:03] - * [08:11] | GPP[08:11] | GFX[15:12] - * [12:15] | n/a | GFX[11:08] - * [16:23] | GFX[00:07] | GFX[07:0] + * logical | physical + * --------|------------ + * [00:03] | GPP[03:00] * * Different ports mustn't overlap or be assigned to the same lane(s). Within * ports with the same width the one with a higher start logical lane number * needs to be assigned to a higher PCIe root port number; ports of the same * size don't have to be assigned to consecutive PCIe root ports though. - * - * Lanes 2 and 3 can be mapped to the SATA controller on all packages; the FT6 - * platform additionally supports mapping lanes 8 and 9 to a SATA controller. - * On embedded SKUs lanes 0 and 1 can be mapped to the Gigabit Ethernet - * controllers. */ typedef struct __packed { uint8_t engine_type; // See dxio_engine_type -- To view, visit https://review.coreboot.org/c/coreboot/+/63121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Gerrit-Change-Number: 63121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/63120 to review the following change. Change subject: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types ...................................................................... util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types Compared to Cezanne, the Sabrina SoC has a 3 additional PSP firmware table entries, so add those as a preparation for Sabrina support. Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/data_parse.c 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/63120/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 8023595..263336a 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -260,6 +260,9 @@ { .type = AMD_FW_SPL, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_DMCU_ERAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_RPMC_NVRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_ABL0, .level = PSP_BOTH | PSP_LVL2_AB }, diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index 70afe3c..ff2f63b 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -54,6 +54,9 @@ AMD_FW_SPL = 0x55, AMD_FW_DMCU_ERAM = 0x58, AMD_FW_DMCU_ISR = 0x59, + AMD_FW_MSMU = 0x5a, + AMD_FW_SPIROM_CFG = 0x5c, + AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_FW_IMC = 0x200, /* Large enough to be larger than the top BHD entry type. */ AMD_FW_GEC, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index e883d17..09b975d 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -306,6 +306,15 @@ } else if (strcmp(fw_name, "DMCUINTVECTORSDCN21_FILE") == 0) { fw_type = AMD_FW_DMCU_ISR; subprog = 0; + } else if (strcmp(fw_name, "MSMU_FILE") == 0) { + fw_type = AMD_FW_MSMU; + subprog = 0; + } else if (strcmp(fw_name, "DMCUB_FILE") == 0) { + fw_type = AMD_FW_DMCUB; + subprog = 0; + } else if (strcmp(fw_name, "SPIROM_CONFIG_FILE") == 0) { + fw_type = AMD_FW_SPIROM_CFG; + subprog = 0; } else if (strcmp(fw_name, "PSP_KVM_ENGINE_DUMMY_FILE") == 0) { fw_type = AMD_FW_KVM_IMAGE; subprog = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/63120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Gerrit-Change-Number: 63120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-MessageType: newchange

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Change in coreboot[master]: include/efi: Add EFI Status code definitions
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63006 ) Change subject: include/efi: Add EFI Status code definitions ...................................................................... include/efi: Add EFI Status code definitions This patch adds EFI status code macros in `efi_datatype.h` to implement FSP debug event handler natively in coreboot. Added `PiStatusCode.h` and `StatusCodeDataTypeId.h` files for `UDK base >= 2017`, as these files were added with UDK version 2017. BUG=b:225544587 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63006 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/efi/efi_datatype.h 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 5415ae8..581193a 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -7,13 +7,23 @@ #include <Uefi/UefiBaseType.h> #if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION +#include <Guid/StatusCodeDataTypeId.h> #include <Pi/PiPeiCis.h> +#include <Pi/PiStatusCode.h> #include <Protocol/MpService.h> /* Data structure for EFI_PEI_SERVICE. */ typedef EFI_PEI_SERVICES efi_pei_services; /* Structure that describes information about a logical CPU. */ typedef EFI_PROCESSOR_INFORMATION efi_processor_information; +/* Status code type definition */ +typedef EFI_STATUS_CODE_TYPE efi_status_code_type_t; +/* Status value type definition */ +typedef EFI_STATUS_CODE_VALUE efi_status_code_value_t; +/* Status data type definition */ +typedef EFI_STATUS_CODE_DATA efi_status_code_data_t; +/* Status string data type definition */ +typedef EFI_STATUS_CODE_STRING_DATA efi_status_code_string_data; #endif /* Basic Data types */ @@ -47,6 +57,8 @@ typedef EFI_STATUS efi_return_status_t; /* Data structure for EFI_PHYSICAL_ADDRESS */ typedef EFI_PHYSICAL_ADDRESS efi_physical_address; +/* 128-bit buffer containing a unique identifier value */ +typedef EFI_GUID efi_guid_t; /* * The function prototype for invoking a function on an 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2debb6a50581456783dc9f22f892f8f92a25509 Gerrit-Change-Number: 63006 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63010 ) Change subject: include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION ...................................................................... include/efi: Add correct header file for EFI_PROCESSOR_INFORMATION This patch resolves compilation issue of including `efi_datatype.h` in other stage files due to unresolved EFI_PROCESSOR_INFORMATION macro definition. EFI_PROCESSOR_INFORMATION defined in `Protocol/MpService.h` hence, included to resolve compilation issue. TEST=Able to build brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Reviewed-on: https://review.coreboot.org/c/coreboot/+/63010 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/include/efi/efi_datatype.h 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index 7eefad3..5415ae8 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -8,6 +8,7 @@ #if CONFIG_UDK_VERSION >= CONFIG_UDK_2017_VERSION #include <Pi/PiPeiCis.h> +#include <Protocol/MpService.h> /* Data structure for EFI_PEI_SERVICE. */ typedef EFI_PEI_SERVICES efi_pei_services; 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/63010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c0ca4f8876e46f1748ffc9e3b90de00ead80ebd Gerrit-Change-Number: 63010 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/mediatek/i2c.c: Remove unused variables
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63023 ) Change subject: soc/mediatek/i2c.c: Remove unused variables ...................................................................... soc/mediatek/i2c.c: Remove unused variables Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63023 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/soc/mediatek/common/i2c.c 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved Rex-BC Chen: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/common/i2c.c b/src/soc/mediatek/common/i2c.c index b4386b9..ab7b0de 100644 --- a/src/soc/mediatek/common/i2c.c +++ b/src/soc/mediatek/common/i2c.c @@ -496,7 +496,6 @@ uint32_t max_clk_div = MAX_CLOCK_DIV; uint32_t clk_src, clk_div, step_cnt, sample_cnt; uint32_t l_step_cnt, l_sample_cnt; - uint32_t timing_reg_value, ltiming_reg_value; struct mtk_i2c *bus_ctrl; if (bus >= I2C_BUS_NUMBER) { @@ -516,27 +515,19 @@ &l_step_cnt, &l_sample_cnt)) continue; - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - /* Set the high speed mode register */ if (mtk_i2c_calculate_speed(bus, clk_src, speed, &step_cnt, &sample_cnt)) continue; - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt | - (sample_cnt << 12) | (step_cnt << 9); bus_ctrl->ac_timing.inter_clk_div = (clk_div - 1) << 8 | (clk_div - 1); } else { if (mtk_i2c_calculate_speed(bus, clk_src, speed, &l_step_cnt, &l_sample_cnt)) continue; - timing_reg_value = (l_sample_cnt << 8) | l_step_cnt; - /* Disable the high speed transaction */ bus_ctrl->ac_timing.hs = I2C_TIME_CLR_VALUE; - - ltiming_reg_value = (l_sample_cnt << 6) | l_step_cnt; } break; -- To view, visit https://review.coreboot.org/c/coreboot/+/63023 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa643feb76530cc74acf4d714d8a7f96709be1cf Gerrit-Change-Number: 63023 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: libpayload/vboot: Fix include paths fixup macro
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63002 ) Change subject: libpayload/vboot: Fix include paths fixup macro ...................................................................... libpayload/vboot: Fix include paths fixup macro Include paths fixup macro for vboot was broken and was adding unnecessary prefix to paths from $(coreboottop). This patch adds correct filters to fix this behavior. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/63002 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/vboot/Makefile.inc 1 file changed, 4 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/vboot/Makefile.inc b/payloads/libpayload/vboot/Makefile.inc index bd1afa8..3ec3278 100644 --- a/payloads/libpayload/vboot/Makefile.inc +++ b/payloads/libpayload/vboot/Makefile.inc @@ -8,10 +8,11 @@ tlcl-objs += $(TLCL_LIB) kconfig-to-binary=$(if $(strip $(1)),1,0) -vboot-fixup-includes = $(patsubst -I%,-I$(top)/%,\ +vboot-fixup-includes = $(filter -I$(coreboottop)/%, $(1)) \ + $(patsubst -I%,-I$(top)/%,\ $(patsubst include/%.h,$(top)/include/%.h,\ - $(filter-out -I$(obj),$(1)))) - + $(filter-out -I$(obj),\ + $(filter-out -I$(coreboottop)/%,$(1))))) ifeq ($(CONFIG_LP_ARCH_MOCK),) VBOOT_CFLAGS += $(call vboot-fixup-includes,$(CFLAGS)) VBOOT_CFLAGS += -I$(abspath $(obj)) -- To view, visit https://review.coreboot.org/c/coreboot/+/63002 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I264e715fa879a4e56b6e5f5423916298e8780a2b Gerrit-Change-Number: 63002 Gerrit-PatchSet: 3 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: $top/Makefile.inc: Move common folder before other sibling ones
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62750 ) Change subject: $top/Makefile.inc: Move common folder before other sibling ones ...................................................................... $top/Makefile.inc: Move common folder before other sibling ones Putting src/soc/*/common before src/soc/*/*, and src/superio/common before src/superio/*,(which is already moved but with duplicated folder "common") can make the variables in common Makefile get the expected value before they are used in other subdirs. The later "*" also contains "common", which needs to be eliminated by "filter-out". Then we can put some common variables from all the subdir Makefile.inc to the common Makefile.inc to reduce code redundancy. Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62750 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index ec2d097..929c236 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -81,8 +81,9 @@ # root source directories of coreboot subdirs-y := src/lib src/commonlib/ src/console src/device src/acpi src/superio/common subdirs-y += src/ec/acpi $(wildcard src/ec/*/*) $(wildcard src/southbridge/*/*) -subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/*) $(wildcard src/northbridge/*/*) -subdirs-y += $(wildcard src/superio/*) $(wildcard src/superio/*/*) +subdirs-y += $(wildcard src/soc/*) $(wildcard src/soc/*/common) $(filter-out $(wildcard src/soc/*/common),$(wildcard src/soc/*/*)) +subdirs-y += $(wildcard src/northbridge/*/*) +subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildcard src/superio/*/*) subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool -- To view, visit https://review.coreboot.org/c/coreboot/+/62750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99597af22cac6d12aaef348789664cd7db02ba06 Gerrit-Change-Number: 62750 Gerrit-PatchSet: 11 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63033 ) Change subject: mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size ...................................................................... mb/google/skyrim: Increase RW_MRC_CACHE FMAP region size ABL generates memory training data whose size is ~80KiB. So increase the RW_MRC_CACHE region size to accommodate that. BUG=b:224618411 TEST=Build and boot to payload in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63033 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/skyrim/chromeos.fmd 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Raul Rangel: Looks good to me, approved Jon Murphy: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/skyrim/chromeos.fmd b/src/mainboard/google/skyrim/chromeos.fmd index a6dbc2c..c114c03 100644 --- a/src/mainboard/google/skyrim/chromeos.fmd +++ b/src/mainboard/google/skyrim/chromeos.fmd @@ -1,6 +1,6 @@ FLASH@0xFF000000 16M { SI_BIOS { - RW_MRC_CACHE(PRESERVE) 64K + RW_MRC_CACHE(PRESERVE) 96K RW_SECTION_A 3M { VBLOCK_A 8K FW_MAIN_A(CBFS) -- To view, visit https://review.coreboot.org/c/coreboot/+/63033 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2040026a1fe2b3f760724023e2e252e137b31c8 Gerrit-Change-Number: 63033 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/lint/checkpatch: Update commit message & subject line limits
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63029 ) Change subject: util/lint/checkpatch: Update commit message & subject line limits ...................................................................... util/lint/checkpatch: Update commit message & subject line limits The commit message has a (soft) line length limit of 72 characters and the subject has a (soft) line limit of 65 characters. This change updates checkpatch to warn at those limits. Note that neither of these are hard limits because git & gerrit can both handle longer lines, it just doesn't look good. Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712 Signed-off-by: Martin Roth <martin(a)coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63029 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/lint/checkpatch.pl 1 file changed, 15 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, approved Felix Singer: Looks good to me, but someone else must approve diff --git a/util/lint/checkpatch.pl b/util/lint/checkpatch.pl index 3cf249c..9355186 100755 --- a/util/lint/checkpatch.pl +++ b/util/lint/checkpatch.pl @@ -2265,7 +2265,6 @@ my $in_commit_log = 0; #Scanning lines before patch my $has_commit_log = 0; #Encountered lines before patch my $commit_log_possible_stack_dump = 0; - my $commit_log_long_line = 0; my $commit_log_has_diff = 0; my $reported_maintainer_file = 0; my $non_utf8_charset = 0; @@ -2658,10 +2657,9 @@ $commit_log_possible_stack_dump = 1; } -# coreboot: The line lengeth limit is 72 -# Check for line lengths > 72 in commit log, warn once - if ($in_commit_log && !$commit_log_long_line && - length($line) > 72 && +# coreboot: The line length limit is 72 +# Check for line lengths > 72 in commit log + if ($in_commit_log && length($line) > 72 && !($line =~ /^\s*[a-zA-Z0-9_\/\.]+\s+\|\s+\d+/ || # file delta changes $line =~ /^\s*(?:[\w\.\-\+]*\/)++[\w\.\-\+]+:/ || @@ -2671,7 +2669,18 @@ $commit_log_possible_stack_dump)) { WARN("COMMIT_LOG_LONG_LINE", "Possible unwrapped commit description (prefer a maximum 72 chars per line)\n" . $herecurr); - $commit_log_long_line = 1; + } + +# coreboot: The line subject limit is 65 +# Check for line lengths > 65 in commit subject + if ($in_header_lines && + $line =~ /^Subject: /) { + $line = $line.$rawlines[$linenr]; + $line =~ s/^Subject: \[PATCH\] //; + if (length($line) > 65) { + WARN("COMMIT_LOG_LONG_LINE", + "Possible long commit subject (prefer a maximum 65 characters)\n" . $herecurr); + } } # Reset possible stack dump if a blank line is found -- To view, visit https://review.coreboot.org/c/coreboot/+/63029 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ef131a65254e2b184b05e0215969aef97e12712 Gerrit-Change-Number: 63029 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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