coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jon Murphy, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63119 ) Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/63119/comment/20ceb8b2_7429525d PS2, Line 34: select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN > i'd say that this should go into soc/amd/sabrina/kconfig, since this will likely affect all boards u […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 20:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63122 ) Change subject: soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode ...................................................................... soc/amd/sabrina: Donot clear Port80 enable bit in ESPI Decode BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae --- M src/soc/amd/sabrina/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/63122/1 diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index b393381..8ed0a56 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -49,6 +49,7 @@ select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_DATA_FABRIC + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_I2C -- To view, visit https://review.coreboot.org/c/coreboot/+/63122 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae Gerrit-Change-Number: 63122 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian. Hello build bot (Jenkins), Raul Rangel, Jon Murphy, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63119 to look at the new patch set (#3). Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... mb/google/skyrim: Disable PSP postcodes BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63119/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume
by 9elements QA (Code Review) 25 Mar '22

25 Mar '22

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63088 ) Change subject: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... Patch Set 2: Automatic boot test returned (PASS/FAIL/TOTAL): 10 / 1 / 11 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES_ and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96997 PASS: x86_32 "Hermes CFL" , build config PRODRIVE_HERMES and payload TianoCore_UefiPayloadPkg : https://lava.9esec.io/r/96996 PASS: x86_32 "ThinkPad T500" , build config LENOVO_T500 and payload SeaBIOS : https://lava.9esec.io/r/96995 PASS: x86_32 "HP Z220 SFF Workstation" , build config HP_Z220_SFF_WORKSTATION and payload LinuxBoot_BB_kexec : https://lava.9esec.io/r/96994 FAIL: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload TianoCore : https://lava.9esec.io/r/96993 PASS: x86_64 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC.X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96992 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload TianoCore : https://lava.9esec.io/r/96991 PASS: x86_32 "HP Compaq 8200 Elite SFF PC" , build config HP_COMPAQ_8200_ELITE_SFF_PC and payload SeaBIOS : https://lava.9esec.io/r/96990 PASS: x86_64 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_X86_64 and payload SeaBIOS : https://lava.9esec.io/r/96989 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ASAN and payload SeaBIOS : https://lava.9esec.io/r/96988 PASS: x86_32 "QEMU x86 i440fx/piix4" , build config EMULATION_QEMU_X86_I440FX_ and payload SeaBIOS : https://lava.9esec.io/r/96987 Please note: This test is under development and might not be accurate at all! -- To view, visit https://review.coreboot.org/c/coreboot/+/63088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Gerrit-Change-Number: 63088 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 20:22:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: vendorcode/amd/cimx/sb900: No current users in the tree
by Arthur Heymans (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Arthur Heymans, Felix Held. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63047 ) Change subject: vendorcode/amd/cimx/sb900: No current users in the tree ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/63047/comment/7107cb83_0eb10c9e PS1, Line 7: vendorcode/amd/cimx/sb900: No current users in the tree > maybe state in the first description line that this patch drops the code due to it being unused, so that both the what and the why are answered Wow, that's a bad commit message indeed ^^. Thanks for reviewing, I'll fix it :-) -- To view, visit https://review.coreboot.org/c/coreboot/+/63047 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4374360c211593a8468b6226f3d1729885b533e0 Gerrit-Change-Number: 63047 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 20:22:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Add DXIO descriptors
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Raul Rangel, Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62903 ) Change subject: mb/google/skyrim: Add DXIO descriptors ...................................................................... Patch Set 13: Code-Review+2 (2 comments) File src/mainboard/google/skyrim/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/62903/comment/8f5be738_a847a1f3 PS8, Line 38: .start_logical_lane = 2, : .end_logical_lane = 3, > I was able to boot to the OS with this patch, so I think it's correct? Is there anything else to ch […] since it works, i'm ok with keeping this like it is for now https://review.coreboot.org/c/coreboot/+/62903/comment/76a0967f_cbacd848 PS8, Line 102: { /* DDI2 - DP (type C) */ > I'm not sure how to test this in our current configuration, but this CL is blocking our ability to b […] i'm ok with revisiting this later. i guess the issue we're running into here which requires the 5th ddi descriptor is that the upds still have 5 ddi descriptors and the default connector type is DDI_DP. only specifying 4 descriptors here likely results in the 5th keeping the default and since the soc only supports 4 ddi ports, that will make some other part of the firmware unhappy -- To view, visit https://review.coreboot.org/c/coreboot/+/62903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib68cf3d64641b006e0f2c4805af22b44a505a0d1 Gerrit-Change-Number: 62903 Gerrit-PatchSet: 13 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 20:21:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jon Murphy <jpmurphy(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62930 ) Change subject: mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts ...................................................................... mb/google/guybrush/var/dewatt: Use exclusive SPD IDs for Samsung parts Parts K4U6E3S4AB-MGCL and K4UBE3D4AB-MGCL require special handling. This commit assigns them exclusive IDs 9 and 11 to facilitate this. BUG=b:224884904 Signed-off-by: Robert Zieba <robertzieba(a)google.com> Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc M src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt M src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt 3 files changed, 14 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc index 02eafcb..c4e409d 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/Makefile.inc @@ -5,6 +5,14 @@ SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 0(0b0000) Parts = MT53E1G32D2NP-046 WT:A -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, K4U6E3S4AB-MGCL, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 1(0b0001) Parts = MT53E512M32D2NP-046 WT:F, H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H54G46CYRBX267, MT53E512M32D1NP-046 WT:B SPD_SOURCES += spd/lp4x/set-1/spd-9.hex # ID = 2(0b0010) Parts = NT6AP256T32AV-J1 -SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247, K4UBE3D4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 3(0b0011) Parts = MT53E1G32D2NP-046 WT:B, H9HCNNNCPMMLXR-NEE, K4UBE3D4AA-MGCR, H54G56CYRBX247 +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 4(0b0100) +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 5(0b0101) +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 6(0b0110) +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 7(0b0111) +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 8(0b1000) +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 9(0b1001) Parts = K4U6E3S4AB-MGCL +SPD_SOURCES += spd/lp4x/set-1/spd-empty.hex # ID = 10(0b1010) +SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 11(0b1011) Parts = K4UBE3D4AB-MGCL diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt index d574a6f4..48d94b3 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/dram_id.generated.txt @@ -13,8 +13,8 @@ K4U6E3S4AA-MGCR 1 (0001) H9HCNNNCPMMLXR-NEE 3 (0011) K4UBE3D4AA-MGCR 3 (0011) -K4U6E3S4AB-MGCL 1 (0001) +K4U6E3S4AB-MGCL 9 (1001) H54G46CYRBX267 1 (0001) MT53E512M32D1NP-046 WT:B 1 (0001) H54G56CYRBX247 3 (0011) -K4UBE3D4AB-MGCL 3 (0011) +K4UBE3D4AB-MGCL 11 (1011) diff --git a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt index 298e58b..9d79210 100644 --- a/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt +++ b/src/mainboard/google/guybrush/variants/dewatt/memory/mem_parts_used.txt @@ -7,8 +7,8 @@ K4U6E3S4AA-MGCR H9HCNNNCPMMLXR-NEE K4UBE3D4AA-MGCR -K4U6E3S4AB-MGCL +K4U6E3S4AB-MGCL,*9 H54G46CYRBX267 MT53E512M32D1NP-046 WT:B H54G56CYRBX247 -K4UBE3D4AB-MGCL +K4UBE3D4AB-MGCL,*11 -- To view, visit https://review.coreboot.org/c/coreboot/+/62930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01ea1442b20849a404cf397614c25a441cc84c4b Gerrit-Change-Number: 62930 Gerrit-PatchSet: 7 Gerrit-Owner: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: Bhanu Prakash Maiya <bhanumaiya(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Peers <epeers(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vendorcode/amd/pi: Fix building with clang
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63048 ) Change subject: vendorcode/amd/pi: Fix building with clang ...................................................................... vendorcode/amd/pi: Fix building with clang Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63048 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/vendorcode/amd/pi/Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 75de398..9b4659e 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -62,6 +62,7 @@ AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include AGESA_CFLAGS += -march=amdfam10 -mno-3dnow +AGESA_CFLAGS += -Wno-pragma-pack AGESA_CFLAGS += -fno-strict-aliasing -D__LIBAGESA__ CFLAGS_x86_32 += $(AGESA_CFLAGS) CFLAGS_x86_64 += $(AGESA_CFLAGS) -- To view, visit https://review.coreboot.org/c/coreboot/+/63048 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82913de07acc13af2f5f2c67853e112fb3c66319 Gerrit-Change-Number: 63048 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/cimx/sb800: Fix building with clang
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63046 ) Change subject: amd/cimx/sb800: Fix building with clang ...................................................................... amd/cimx/sb800: Fix building with clang These are all set but unused variable problems. Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63046 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/vendorcode/amd/cimx/sb800/AMDSBLIB.c M src/vendorcode/amd/cimx/sb800/AZALIA.c M src/vendorcode/amd/cimx/sb800/DISPATCHER.c M src/vendorcode/amd/cimx/sb800/EC.c M src/vendorcode/amd/cimx/sb800/GEC.c M src/vendorcode/amd/cimx/sb800/SBCMN.c M src/vendorcode/amd/cimx/sb800/SBMAIN.c M src/vendorcode/amd/cimx/sb800/SBPort.c M src/vendorcode/amd/cimx/sb800/SMM.c 9 files changed, 7 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c index a5d92ad..26d9110 100644 --- a/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c +++ b/src/vendorcode/amd/cimx/sb800/AMDSBLIB.c @@ -101,8 +101,6 @@ IN UINT8 OpFlag ) { - UINT8 Temp; - Temp = OpFlag; RWIO (0xcf9, AccWidthUint8, 0x0, 0x06); } diff --git a/src/vendorcode/amd/cimx/sb800/AZALIA.c b/src/vendorcode/amd/cimx/sb800/AZALIA.c index 1d7d0f9..d9e1f13 100644 --- a/src/vendorcode/amd/cimx/sb800/AZALIA.c +++ b/src/vendorcode/amd/cimx/sb800/AZALIA.c @@ -270,13 +270,11 @@ UINT8 dbTempVariable; UINT16 dwTempVariable; UINT32 ddBAR0; - UINT32 ddTempVariable; dbEnableAzalia = 0; dbChannelNum = 0; dbTempVariable = 0; dwTempVariable = 0; ddBAR0 = 0; - ddTempVariable = 0; if ( pConfig->AzaliaController == 1 ) { return; @@ -509,4 +507,3 @@ ++tempAzaliaCodecEntryPtr; } } - diff --git a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c index 1c86c58..faec104 100644 --- a/src/vendorcode/amd/cimx/sb800/DISPATCHER.c +++ b/src/vendorcode/amd/cimx/sb800/DISPATCHER.c @@ -88,9 +88,6 @@ { AGESA_STATUS Status; - UINT64 tdValue; - tdValue = 0x32314130384253ULL; - Status = AGESA_UNSUPPORTED; saveConfigPointer (pConfig); diff --git a/src/vendorcode/amd/cimx/sb800/EC.c b/src/vendorcode/amd/cimx/sb800/EC.c index 9e70e8b..c407537 100644 --- a/src/vendorcode/amd/cimx/sb800/EC.c +++ b/src/vendorcode/amd/cimx/sb800/EC.c @@ -109,8 +109,8 @@ IN AMDSBCFG* pConfig ) { - AMDSBCFG* pTmp; // dummy code - pTmp = pConfig; + /* AMDSBCFG* pTmp; // dummy code */ + /* pTmp = pConfig; */ } /** @@ -125,7 +125,7 @@ IN AMDSBCFG* pConfig ) { - AMDSBCFG* pTmp; // dummy code - pTmp = pConfig; + /* AMDSBCFG* pTmp; // dummy code */ + /* pTmp = pConfig; */ } #endif diff --git a/src/vendorcode/amd/cimx/sb800/GEC.c b/src/vendorcode/amd/cimx/sb800/GEC.c index d1715bc..ec2dd6e 100644 --- a/src/vendorcode/amd/cimx/sb800/GEC.c +++ b/src/vendorcode/amd/cimx/sb800/GEC.c @@ -137,9 +137,7 @@ IN AMDSBCFG* pConfig ) { - if ( !pConfig->GecConfig == 0) { - return; //return if GEC controller is disabled. - } + /* if ( !pConfig->GecConfig == 0) { */ + /* return; //return if GEC controller is disabled. */ + /* } */ } - - diff --git a/src/vendorcode/amd/cimx/sb800/SBCMN.c b/src/vendorcode/amd/cimx/sb800/SBCMN.c index 3d4ce82..149e1de 100644 --- a/src/vendorcode/amd/cimx/sb800/SBCMN.c +++ b/src/vendorcode/amd/cimx/sb800/SBCMN.c @@ -330,14 +330,11 @@ UINT32 abValue; UINT16 dwTempVar; CPUID_DATA CpuId; - UINT8 cimNativepciesupport; UINT8 cimIrConfig; UINT8 Data; - cimNativepciesupport = (UINT8) pConfig->NativePcieSupport; cimIrConfig = (UINT8) pConfig->IrConfig; #if SB_CIMx_PARAMETER == 0 - cimNativepciesupport = cimNativepciesupportDefault; cimIrConfig = cimIrConfigDefault; #endif @@ -518,8 +515,6 @@ UINT8 dbPortStatus; UINT8 cimSpreadSpectrum; UINT32 cimSpreadSpectrumType; - AMDSBCFG* pTmp; - pTmp = pConfig; cimSpreadSpectrum = pConfig->SpreadSpectrum; cimSpreadSpectrumType = pConfig->BuildParameters.SpreadSpectrumType; @@ -606,13 +601,11 @@ { UINT32 cimResetCpuOnSyncFlood; ABTBLENTRY *pAbTblPtr; - AMDSBCFG* Temp; cimResetCpuOnSyncFlood = pConfig->ResetCpuOnSyncFlood; #if SB_CIMx_PARAMETER == 0 cimResetCpuOnSyncFlood = cimResetCpuOnSyncFloodDefault; #endif - Temp = pConfig; if ( pConfig->SbPcieOrderRule ) { pAbTblPtr = (ABTBLENTRY *) FIXUP_PTR (&SbPcieOrderRule[0]); abcfgTbl (pAbTblPtr); @@ -800,9 +793,7 @@ IN AMDSBCFG* pConfig ) { - AMDSBCFG* Temp; UINT8 dbValue; - Temp = pConfig; //RPR C-State and VID/FID Change dbValue = getNumberOfCpuCores (); if (dbValue > 1) { diff --git a/src/vendorcode/amd/cimx/sb800/SBMAIN.c b/src/vendorcode/amd/cimx/sb800/SBMAIN.c index 0e10a2a..04716bc 100644 --- a/src/vendorcode/amd/cimx/sb800/SBMAIN.c +++ b/src/vendorcode/amd/cimx/sb800/SBMAIN.c @@ -218,8 +218,6 @@ { // Commented the following code since we need to leave the IRQ1/12 filtering enabled always as per latest // recommendation in RPR. This is required to fix the keyboard stuck issue when playing games under Windows - AMDSBCFG* pTmp; //lx-dummy for /W4 build - pTmp = pConfig; // Disable Power Button SMI RWMEM (ACPI_MMIO_BASE + SMI_BASE + SB_SMI_REGB2, AccWidthUint8, ~(BIT4 + BIT5), 0); @@ -250,5 +248,3 @@ return Result; } - - diff --git a/src/vendorcode/amd/cimx/sb800/SBPort.c b/src/vendorcode/amd/cimx/sb800/SBPort.c index ba6c8f0..ae1d779 100644 --- a/src/vendorcode/amd/cimx/sb800/SBPort.c +++ b/src/vendorcode/amd/cimx/sb800/SBPort.c @@ -141,14 +141,12 @@ UINT8 dbCg2WR; UINT8 dbCg1Pll; UINT8 cimNbSbGen2; - UINT8 cimSataMode; UINT8 cimSpiFastReadEnable; UINT8 cimSpiFastReadSpeed; UINT8 cimSioHwmPortEnable; UINT8 SataPortNum; cimNbSbGen2 = pConfig->NbSbGen2; - cimSataMode = pConfig->SATAMODE.SataModeReg; // Adding Fast Read Function support if (pConfig->BuildParameters.SpiFastReadEnable != 0 ) { cimSpiFastReadEnable = (UINT8) pConfig->BuildParameters.SpiFastReadEnable; diff --git a/src/vendorcode/amd/cimx/sb800/SMM.c b/src/vendorcode/amd/cimx/sb800/SMM.c index 894ec2a..1d501e5 100644 --- a/src/vendorcode/amd/cimx/sb800/SMM.c +++ b/src/vendorcode/amd/cimx/sb800/SMM.c @@ -63,8 +63,6 @@ IN AMDSBCFG* pConfig ) { - AMDSBCFG* pTmp; //lx-dummy for /W4 build - pTmp = pConfig; } /** @@ -79,8 +77,3 @@ ) { } - - - - - -- To view, visit https://review.coreboot.org/c/coreboot/+/63046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Gerrit-Change-Number: 63046 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: amd/cimx/sb800: Fix building with clang
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Arthur Heymans. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63046 ) Change subject: amd/cimx/sb800: Fix building with clang ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63046 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I40aaa1d1cdd90731a23142f1f7a0f67a45915f25 Gerrit-Change-Number: 63046 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Fri, 25 Mar 2022 20:12:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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