coreboot-gerrit March 2022

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Change in coreboot[master]: vendorcode/amd/agesa: Add CFLAGS required by CLANG
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63040 ) Change subject: vendorcode/amd/agesa: Add CFLAGS required by CLANG ...................................................................... vendorcode/amd/agesa: Add CFLAGS required by CLANG Vendorcode is messy so instead of trying to fix the warnings thrown by clang ignore them on AGESA platforms. Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63040 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/vendorcode/amd/agesa/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index b96af84..73a87a3 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -11,6 +11,11 @@ libagesa-generic-ccopts += -D__LIBAGESA__ libagesa-generic-ccopts += -fno-zero-initialized-in-bss libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +libagesa-generic-ccopts += -Wno-pragma-pack -Wno-unused-but-set-variable +libagesa-generic-ccopts += -Wno-implicit-fallthrough + +romstage-generic-ccopts += -Wno-pragma-pack +ramstage-generic-ccopts += -Wno-pragma-pack AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-strict-aliasing -- To view, visit https://review.coreboot.org/c/coreboot/+/63040 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I378571c2b7272901761c786c6daec0a403155d4c Gerrit-Change-Number: 63040 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63024 ) Change subject: sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields ...................................................................... sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields Clang complains about this. Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h 2 files changed, 13 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 3ec68ae..ec7b977 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -55,17 +55,17 @@ /* IDE configuration */ uint8_t sata_port_map : 6; - int sata_clock_request : 1; - int sata_traffic_monitor : 1; + unsigned int sata_clock_request : 1; + unsigned int sata_traffic_monitor : 1; - int c4onc3_enable:1; - int c5_enable : 1; - int c6_enable : 1; + unsigned int c4onc3_enable:1; + unsigned int c5_enable : 1; + unsigned int c6_enable : 1; - int throttle_duty : 3; + unsigned int throttle_duty : 3; /* Bit mask to tell whether a PCIe slot is implemented as slot. */ - int pcie_slot_implemented : 6; + unsigned int pcie_slot_implemented : 6; /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ struct { diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index e9632d2..ae31d4f 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -42,16 +42,16 @@ /* IDE configuration */ uint8_t sata_port_map : 6; - int sata_clock_request : 1; + unsigned int sata_clock_request : 1; - int c4onc3_enable:1; - int c5_enable : 1; - int c6_enable : 1; + unsigned int c4onc3_enable:1; + unsigned int c5_enable : 1; + unsigned int c6_enable : 1; - int throttle_duty : 3; + unsigned int throttle_duty : 3; /* Bit mask to tell whether a PCIe slot is implemented as slot. */ - int pcie_slot_implemented : 6; + unsigned int pcie_slot_implemented : 6; /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/63024 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379 Gerrit-Change-Number: 63024 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: nb/intel/gm45/pm.c: Make clang happy
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62172 ) Change subject: nb/intel/gm45/pm.c: Make clang happy ...................................................................... nb/intel/gm45/pm.c: Make clang happy Clang complains that the terniary '?' operator is executed before the bitwise '|'. This is true and desired in this case. Being explicit about won't hurt however. Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62172 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/pm.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/pm.c b/src/northbridge/intel/gm45/pm.c index f1b7abc..656a632 100644 --- a/src/northbridge/intel/gm45/pm.c +++ b/src/northbridge/intel/gm45/pm.c @@ -171,7 +171,7 @@ mchbar_setbits32(0xf80, 1 << 31); mchbar_write32(0x40, (mchbar_read32(0x40) & ~(0x3f << 24)) | - (sysinfo->cores == 4) ? (1 << 24) : 0); + ((sysinfo->cores == 4) ? (1 << 24) : 0)); mchbar_clrbits32(0x40, 1 << 19); mchbar_setbits32(0x40, 1 << 13); -- To view, visit https://review.coreboot.org/c/coreboot/+/62172 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d1fc1c19e1dab3d1c82e407151eaa46f8c7b03 Gerrit-Change-Number: 62172 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 FSP 2.3 spec introduced new version of NV storage HOB FSP_NON_VOLATILE_STORAGE_HOB2. This new HOB addresses the limitation of FSP_NON_VOLATILE_STORAGE_HOB which can support data length upto 64KB. FSP_NON_VOLATILE_STORAGE_HOB2 allows >64KB of NVS data to be stored by specifying a pointer to the NVS data. FSP_NON_VOLATILE_STORAGE_HOB HOB is deprecated from FSP 2.3 onwards and is maintained for backward compatibility only. This patch implements the parsing method for FSP_NON_VOLATILE_STORAGE_HOB2 HOB structure .The HOB list is first searched for FSP_NON_VOLATILE_STORAGE_HOB2. If not found we continue to search for FSP_NON_VOLATILE_STORAGE_HOB HOB. BUG=b:200113959 TEST=Verified on sapphire rapids and meteor lake FSP platform that introduces FSP_NON_VOLATILE_STORAGE_HOB2 for retrieving MRC cached data. Signed-off-by: Anil Kumar <anil.kumar.k(a)intel.com> Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Reviewed-on: https://review.coreboot.org/c/coreboot/+/59638 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/drivers/intel/fsp2_0/hand_off_block.c M src/drivers/intel/fsp2_0/include/fsp/util.h 2 files changed, 21 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Wonkyu Kim: Looks good to me, approved Tim Wawrzynczak: Looks good to me, but someone else must approve diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index c9c99f9..9144eaa 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -22,6 +22,11 @@ 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, }; +const uint8_t fsp_nv_storage_guid_2[16] = { + 0x8f, 0x78, 0x66, 0x48, 0xa8, 0x6b, 0xd8, 0x47, + 0x83, 0x6, 0xac, 0xf7, 0x7f, 0x55, 0x10, 0x46 +}; + const uint8_t fsp_nv_storage_guid[16] = { 0x02, 0xcf, 0x1a, 0x72, 0x77, 0x4d, 0x2a, 0x4c, 0xb3, 0xdc, 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 @@ -306,6 +311,16 @@ const void *fsp_find_nv_storage_data(size_t *size) { + if (CONFIG(PLATFORM_USES_FSP2_3)) { + const struct fsp_nvs_hob2_data_region_header *hob; + + hob = (const struct fsp_nvs_hob2_data_region_header *) + fsp_find_extension_hob_by_guid(fsp_nv_storage_guid_2, size); + if (hob != NULL) { + *size = hob->nvs_data_length; + return (void *)(uintptr_t)hob->nvs_data_ptr; + } + } return fsp_find_extension_hob_by_guid(fsp_nv_storage_guid, size); } diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 7347034..2687d0d 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -8,6 +8,7 @@ #include <commonlib/region.h> #include <arch/cpu.h> #include <fsp/api.h> +#include <efi/efi_datatype.h> #include <fsp/info_header.h> #include <memrange.h> #include <program_loading.h> @@ -27,6 +28,11 @@ uint16_t length; } __packed; +struct fsp_nvs_hob2_data_region_header { + efi_physical_address nvs_data_ptr; + uint64_t nvs_data_length; +}; + struct fsp_notify_params { enum fsp_notify_phase phase; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 45 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Arthur Heymans, Anil Kumar K, Subrata Banik, Selma Bensaid, Paul Menzel, Tim Wawrzynczak, Andrey Petrov, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59638 ) Change subject: drivers/intel/fsp2_0: Add support for FSP_NON_VOLATILE_STORAGE_HOB2 ...................................................................... Patch Set 44: (1 comment) File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/59638/comment/f219f94b_bb5d513a PS44, Line 32: efi_physical_address > Done can't say that i like this, but since it's in the fsp driver and not common coreboot code i won't object to this -- To view, visit https://review.coreboot.org/c/coreboot/+/59638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27647e9ac1a4902256b3f1c34b60e1f0b787a06e Gerrit-Change-Number: 59638 Gerrit-PatchSet: 44 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Srinidhi N Kaushik <srinidhi.n.kaushik(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Fri, 25 Mar 2022 19:58:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/*/meminit.c: Fix formatted print
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63052 ) Change subject: soc/intel/*/meminit.c: Fix formatted print ...................................................................... soc/intel/*/meminit.c: Fix formatted print This fixes building with clang. Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63052 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/intel/elkhartlake/meminit.c M src/soc/intel/jasperlake/meminit.c 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/soc/intel/elkhartlake/meminit.c b/src/soc/intel/elkhartlake/meminit.c index d6de9a4..fd64c7d 100644 --- a/src/soc/intel/elkhartlake/meminit.c +++ b/src/soc/intel/elkhartlake/meminit.c @@ -12,7 +12,7 @@ { size_t spd_index = spd_info->spd_spec.spd_index; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + printk(BIOS_DEBUG, "SPD INDEX = %zu\n", spd_index); /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); diff --git a/src/soc/intel/jasperlake/meminit.c b/src/soc/intel/jasperlake/meminit.c index 9ec1ffa..9cf5ecb 100644 --- a/src/soc/intel/jasperlake/meminit.c +++ b/src/soc/intel/jasperlake/meminit.c @@ -12,7 +12,7 @@ { size_t spd_index = spd_info->spd_spec.spd_index; - printk(BIOS_DEBUG, "SPD INDEX = %lu\n", spd_index); + printk(BIOS_DEBUG, "SPD INDEX = %zu\n", spd_index); /* Memory leak is ok since we have memory mapped boot media */ assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); -- To view, visit https://review.coreboot.org/c/coreboot/+/63052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2686b0938d34cd66393eb14205c5c8a5b3ba98b Gerrit-Change-Number: 63052 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63120 ) Change subject: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types ...................................................................... Patch Set 1: (1 comment) File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/63120/comment/baf98e7a_d690e5f1 PS1, Line 315: SPIROM_CONFIG_FILE I really hope we can generate this from the coreboot build... -- To view, visit https://review.coreboot.org/c/coreboot/+/63120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Gerrit-Change-Number: 63120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 19:53:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63120 ) Change subject: util/amdfwtool: add MSMU, SPIROM_CFG and DMCUB PSP FW types ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa5aacd53b3c7637f6d5e94b1a8d92bba57ddb9d Gerrit-Change-Number: 63120 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 19:53:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/noncar/memmap.c: Fix formatted print
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63050 ) Change subject: soc/amd/noncar/memmap.c: Fix formatted print ...................................................................... soc/amd/noncar/memmap.c: Fix formatted print Fixes building with clang. Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63050 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/cpu/noncar/memmap.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/cpu/noncar/memmap.c b/src/soc/amd/common/block/cpu/noncar/memmap.c index 8f37f1a..6e35003 100644 --- a/src/soc/amd/common/block/cpu/noncar/memmap.c +++ b/src/soc/amd/common/block/cpu/noncar/memmap.c @@ -64,5 +64,5 @@ { *start = cbmem_add(CBMEM_ID_ACPI_BERT, CONFIG_ACPI_BERT_SIZE); *size = CONFIG_ACPI_BERT_SIZE; - printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%lx\n", *start, *size); + printk(BIOS_INFO, "Reserved BERT region base: %p, size: 0x%zx\n", *start, *size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/63050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7027f3681e18b8ca0d2f0c899412806082846463 Gerrit-Change-Number: 63050 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63121 ) Change subject: vc/amd/fsp/sabrina/platform_descriptor: update DXIO lane mapping table ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63121 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5aa3abf21e20bbe846f1acfdc2755e97eca1e63 Gerrit-Change-Number: 63121 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 19:52:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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