coreboot-gerrit March 2022

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Change in coreboot[master]: mb/google/brya/{}: Add SBU orientation property for Type C Mux
by Prashant Malani (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Subrata Banik, Maulik V Vaghela, Tim Wawrzynczak, Meera Ravindranath, Nick Vaccaro, Prashant Malani, Rajat Jain. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61622 ) Change subject: mb/google/brya/{}: Add SBU orientation property for Type C Mux ...................................................................... Patch Set 6: (2 comments) File src/mainboard/google/brya/variants/felwinter/overridetree.cb: https://review.coreboot.org/c/coreboot/+/61622/comment/963223a4_a10a49d2 PS6, Line 328: # SBU is fixed, HSL follows CC : register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" Sorry for the late comment here: Why does the other port not need this? Is only this port the one which has a retimer? File src/mainboard/google/brya/variants/taeko/overridetree.cb: https://review.coreboot.org/c/coreboot/+/61622/comment/95e1a5e1_7781fa8d PS6, Line 450: # SBU is fixed, HSL follows CC : register "sbu_orientation" = "TYPEC_ORIENTATION_NORM Does the other port not use a retimer? -- To view, visit https://review.coreboot.org/c/coreboot/+/61622 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f7f9554b75f4d62298aac9938e66c71c3e7cee9 Gerrit-Change-Number: 61622 Gerrit-PatchSet: 6 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Prashant Malani <pmalani(a)google.com> Gerrit-CC: Rajat Jain <rajatja(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-Attention: Rajat Jain <rajatja(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 17:46:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/63118/comment/72e940ac_2f66ef99 PS1, Line 142: ! > Can you swap the blocks so we can remove the negation. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 16:54:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Hello Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/63118 to look at the new patch set (#2). Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... soc/amd/common/block/lpc: Add support to not clear port80 enable SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63118/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63119 ) Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 16:50:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 1: Code-Review+1 (1 comment) File src/soc/amd/common/block/lpc/espi_util.c: https://review.coreboot.org/c/coreboot/+/63118/comment/fc6ccd32_f97c0117 PS1, Line 142: ! Can you swap the blocks so we can remove the negation. -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 16:50:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63119 ) Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... mb/google/skyrim: Disable PSP postcodes Also retain the port80 enable bit in ESPI decode register BUG=b:224618411 TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/63119/1 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index a036fa5..eae6adc 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -29,7 +29,9 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 + select PSP_DISABLE_POSTCODES select SOC_AMD_SABRINA + select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN select SOC_AMD_COMMON_BLOCK_USE_ESPI config CHROMEOS -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Karthik Ramasubramanian (Code Review) 25 Mar '22

25 Mar '22

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... soc/amd/common/block/lpc: Add support to not clear port80 enable SMU locks up sometimes if the port80 enable bit is cleared in the ESPI Decode register. Add a config to choose between clearing the entire ESPI Decode Register vs retaining the port80 enable bit. BUG=None TEST=Build and boot to OS in Skyrim. Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 --- M src/soc/amd/common/block/lpc/Kconfig M src/soc/amd/common/block/lpc/espi_util.c 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/63118/1 diff --git a/src/soc/amd/common/block/lpc/Kconfig b/src/soc/amd/common/block/lpc/Kconfig index 6419269..125f8b3 100644 --- a/src/soc/amd/common/block/lpc/Kconfig +++ b/src/soc/amd/common/block/lpc/Kconfig @@ -42,3 +42,11 @@ help Select this option if mainboard uses eSPI instead of LPC (if supported by platform). + +config SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN + bool + depends on SOC_AMD_COMMON_BLOCK_USE_ESPI + help + SMU will lock up at times if the port80h enable bit is cleared. Select + this option to retain the port80 enable bit while clearing other enable + bits in the ESPI Decode register. diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index c61c61f..5c63169 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -139,7 +139,10 @@ unsigned int idx; /* First turn off all enable bits, then zero base, range, and size registers */ - espi_write16(ESPI_DECODE, 0); + if (!CONFIG(SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN)) + espi_write16(ESPI_DECODE, 0); + else + espi_write16(ESPI_DECODE, (espi_read16(ESPI_DECODE) & ESPI_DECODE_IO_0x80_EN)); for (idx = 0; idx < ESPI_GENERIC_IO_WIN_COUNT; idx++) { espi_write16(espi_io_range_base_reg(idx), 0); -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Adjust FMD file to chromeos.fmd for kano
by Tim Wawrzynczak (Code Review) 25 Mar '22

25 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63086 ) Change subject: mb/google/brya: Adjust FMD file to chromeos.fmd for kano ...................................................................... mb/google/brya: Adjust FMD file to chromeos.fmd for kano The separate FMD file for Kano is no longer required, as it was only required for early prototype testers, and those devices will be retired soon, therefore switch back to the original FMD file. BUG=b:226018550 TEST=Build pass. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/63086 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2599587..b501754 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -123,7 +123,7 @@ default 0x50 config FMDFILE - default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_KANO || BOARD_GOOGLE_BRASK + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-serger.fmd" if BOARD_GOOGLE_BRASK default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-nissa.fmd" if BOARD_GOOGLE_BASEBOARD_NISSA default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" -- To view, visit https://review.coreboot.org/c/coreboot/+/63086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09833039a450fa014e8e501bde9fec6e7ed59c7a Gerrit-Change-Number: 63086 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Grace Kao <grace.kao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Tracy Wu <tracy.wu(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15
by Tim Wawrzynczak (Code Review) 25 Mar '22

25 Mar '22

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63011 ) Change subject: drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15 ...................................................................... drivers/i2c/tpm: Work around missing board_cfg in Ti50 FW under 0.15 Ti50 FW under 0.15 is not support board cfg command which causes I2C errors and entering recovery mode. And ODM stocks are 0.12 pre-flashed. Add workaround for the old Ti50 chip. BUG=b:224650720 TEST=no I2C errors in coreboot. [ERROR] cr50_i2c_read: Address write failed [INFO ] .I2C stop bit not received Signed-off-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63011 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/drivers/i2c/tpm/Kconfig M src/drivers/i2c/tpm/cr50.c M src/mainboard/google/brya/Kconfig 3 files changed, 13 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/drivers/i2c/tpm/Kconfig b/src/drivers/i2c/tpm/Kconfig index dcf9060..0d5f06b 100644 --- a/src/drivers/i2c/tpm/Kconfig +++ b/src/drivers/i2c/tpm/Kconfig @@ -24,6 +24,15 @@ help Board has a generic I2C TPM support +config MAINBOARD_NEEDS_I2C_TI50_WORKAROUND + bool + default n + help + Ti50 FW versions below 0.15 don't support the firmware_version or board_cfg registers, + and trying to access them causes I2C errors. This config will skip accesses to these + registers, and should be selected for boards using Ti50 chips with FW < 0.15. The config + will be removed once all Ti50 stocks are updated to 0.15 or higher. + config DRIVER_TIS_DEFAULT bool depends on I2C_TPM diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index ce2278b..7eb066d 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -500,7 +500,9 @@ printk(BIOS_DEBUG, "cr50 TPM 2.0 (i2c %u:0x%02x id 0x%x)\n", bus, dev_addr, did_vid >> 16); - if (tpm_first_access_this_boot()) { + /* Ti50 FW version under 0.15 doesn't support board cfg command + TODO: remove this flag after all stocks Ti50 uprev to 0.15 or above */ + if (!CONFIG(MAINBOARD_NEEDS_I2C_TI50_WORKAROUND) && tpm_first_access_this_boot()) { /* This is called for the side-effect of printing the version string. */ cr50_get_firmware_version(&ver); cr50_set_board_cfg(); diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 199db11..2599587 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -60,6 +60,7 @@ def_bool n select BOARD_GOOGLE_BRYA_COMMON select CHROMEOS_DRAM_PART_NUMBER_IN_CBI if CHROMEOS + select MAINBOARD_NEEDS_I2C_TI50_WORKAROUND select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW -- To view, visit https://review.coreboot.org/c/coreboot/+/63011 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieec7842ca66b4c690df04a400cebcf45138c745d Gerrit-Change-Number: 63011 Gerrit-PatchSet: 9 Gerrit-Owner: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya: Demote EC check message level from error to warning
by Tim Wawrzynczak (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: John Su, Nick Vaccaro, Eric Lai. Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63099 ) Change subject: mb/google/brya: Demote EC check message level from error to warning ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > @Tim, We probably can ignore CBI command with -3 return. keep other errors. […] You will see this error I think if not all of the CBI fields are set up correctly, e.g. OEM_NAME, make sure all CBI fields are set up correctly and try re-running the test -- To view, visit https://review.coreboot.org/c/coreboot/+/63099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83d3eec6dba7b8cd006b58b93a7c53842ad6ce0a Gerrit-Change-Number: 63099 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 15:38:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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coreboot-gerrit March 2022