coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Fred Reitberger (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Karthik Ramasubramanian. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: > since this is just about one of the fixed ranges and not a configurable one, i'd say that this is a […] Should the other two fixed decode ranges be handled the same way? -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 19:00:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/skyrim: Disable PSP postcodes
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jon Murphy, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63119 ) Change subject: mb/google/skyrim: Disable PSP postcodes ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/skyrim/Kconfig: https://review.coreboot.org/c/coreboot/+/63119/comment/3550b29f_4a4b4c54 PS2, Line 34: select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN i'd say that this should go into soc/amd/sabrina/kconfig, since this will likely affect all boards using this soc -- To view, visit https://review.coreboot.org/c/coreboot/+/63119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73b7ddec50936f7836f915f459ca0bdc0777cb22 Gerrit-Change-Number: 63119 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 18:56:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: since this is just about one of the fixed ranges and not a configurable one, i'd say that this is a good way forward. the configurable ranges should all be set up by coreboot which is still the case here -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Fri, 25 Mar 2022 18:55:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63088 ) Change subject: soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/sabrina/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63088 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index c355a70..9893a8b 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -13,6 +13,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -39,7 +40,10 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63088 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e25075a007505e53962525ec4d9acd2ce6c7ae Gerrit-Change-Number: 63088 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63087 ) Change subject: soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/picasso/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume TEST=builds Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63087 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/picasso/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index de6e9c0..f14ee49 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,6 +10,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> @@ -41,7 +42,10 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63087 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia58000ce9dac5ecb69ca39354f7775524e439bd0 Gerrit-Change-Number: 63087 Gerrit-PatchSet: 2 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63025 ) Change subject: soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume ...................................................................... soc/amd/cezanne/cpu.c: Skip SMMINFO init in S3 resume SMMINFO is already set up in S5, so it should be skipped in S3 resume BUG=b:194990818 TEST=Build guybrush Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/cezanne/cpu.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, but someone else must approve Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index adc99d0..818e4d8 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -11,6 +11,7 @@ #include <cpu/x86/mp.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <acpi/acpi.h> #include <device/device.h> #include <soc/cpu.h> #include <soc/iomap.h> @@ -37,7 +38,10 @@ static void post_mp_init(void) { global_smi_enable(); - apm_control(APM_CNT_SMMINFO); + + /* SMMINFO only needs to be set up when booting from S5 */ + if (!acpi_is_wakeup_s3()) + apm_control(APM_CNT_SMMINFO); } static const struct mp_ops mp_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/63025 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30ee6d7006ddac4dbdae9825bd4fa6eac7fd48cb Gerrit-Change-Number: 63025 Gerrit-PatchSet: 4 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/sabrina: update soft fuse bit 15 definition
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63049 ) Change subject: soc/amd/sabrina: update soft fuse bit 15 definition ...................................................................... soc/amd/sabrina: update soft fuse bit 15 definition For SoC that don't support LPC any more the definition of the PSP soft fuse chain bit 15 has changed. Earlier SoCs that still supported a physical LPC bus used this bit to determine if the I/O port 0x80 POST code are sent to LPC or eSPI. Newer SoCs like Sabrina don't have a physical LPC bus any more and on those this bit selects if the PSP debug output is sent to the SoC's MMIO UART or an UART on I/O port 0x3F8 that the needs to be decoded to eSPI. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Reviewed-on: https://review.coreboot.org/c/coreboot/+/63049 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/sabrina/Kconfig M src/soc/amd/sabrina/Makefile.inc 2 files changed, 2 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig index b393381..8392e2f 100644 --- a/src/soc/amd/sabrina/Kconfig +++ b/src/soc/amd/sabrina/Kconfig @@ -399,8 +399,8 @@ Bit 0: Enable secure debug (Set by PSP_UNLOCK_SECURE_DEBUG) Bit 7: Disable PSP postcodes on Renoir and newer chips only (Set by PSP_DISABLE_PORT80) - Bit 15: PSP post code destination: 0=LPC 1=eSPI - (Set by PSP_INITIALIZE_ESPI) + Bit 15: PSP debug output destination: + 0=SoC MMIO UART, 1=IO port 0x3F8 Bit 29: Disable MP2 firmware loading (Set by PSP_LOAD_MP2_FW) See #55758 (NDA) for additional bit definitions. diff --git a/src/soc/amd/sabrina/Makefile.inc b/src/soc/amd/sabrina/Makefile.inc index 74124d2..b180156 100644 --- a/src/soc/amd/sabrina/Makefile.inc +++ b/src/soc/amd/sabrina/Makefile.inc @@ -97,10 +97,6 @@ PSP_SOFTFUSE_BITS += 7 endif -ifeq ($(CONFIG_PSP_POSTCODES_ON_ESPI),y) -PSP_SOFTFUSE_BITS += 15 -endif - ifeq ($(CONFIG_PSP_UNLOCK_SECURE_DEBUG),y) # Enable secure debug unlock PSP_SOFTFUSE_BITS += 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/63049 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0bffb6efacc585a1d02a0455b32f7cf8662b3232 Gerrit-Change-Number: 63049 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: include/espi.h: Switch to types.h
by Felix Held (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Raul Rangel, Karthikeyan Ramasubramanian. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63092 ) Change subject: include/espi.h: Switch to types.h ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63092 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I78b579de4e3832dd49a18413bf5d03870e347c91 Gerrit-Change-Number: 63092 Gerrit-PatchSet: 2 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Comment-Date: Fri, 25 Mar 2022 18:49:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/moonbuggy: Update GPIOs
by Pablo Ceballos (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Tim Wawrzynczak. Pablo Ceballos has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63014 ) Change subject: mb/google/hatch/moonbuggy: Update GPIOs ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Tim, is there anything else needed to submit this change? I don't have submit permissions. -- To view, visit https://review.coreboot.org/c/coreboot/+/63014 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9cafe81e391bce6ab7ffbe23c2d57b407d146f3 Gerrit-Change-Number: 63014 Gerrit-PatchSet: 1 Gerrit-Owner: Pablo Ceballos <pceballos(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Fri, 25 Mar 2022 18:00:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/lpc: Add support to not clear port80 enable
by Raul Rangel (Code Review) 25 Mar '22

25 Mar '22

Attention is currently required from: Jason Glenesk, Marshall Dawson, Fred Reitberger, Karthik Ramasubramanian, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63118 ) Change subject: soc/amd/common/block/lpc: Add support to not clear port80 enable ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/63118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5ee012ac4858d6dd43827274169edf622a70489 Gerrit-Change-Number: 63118 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 25 Mar 2022 17:50:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2022