Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63183 )
Change subject: util/amdfwtool: use table-relative addressing in ISH case
......................................................................
util/amdfwtool: use table-relative addressing in ISH case
When the image slot header (ISH) is used, the addresses in the PSP and
BIOS directory tables need to be relative to the beginning of the table.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ia61f7c8313d5a1af95c68b9177a53a2f5443552a
---
M util/amdfwtool/amdfwtool.c
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/63183/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 0cfe307..9e7f920 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1798,7 +1798,9 @@
fprintf(stderr, "WARNING: No SOC name specified.\n");
}
- if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN)
+ if (cb_config.need_ish)
+ ctx.address_mode = ADDRESS_MODE_2_REL_TAB;
+ else if (amd_romsig->efs_gen.gen == EFS_SECOND_GEN)
ctx.address_mode = ADDRESS_MODE_1_REL_BIOS;
else
ctx.address_mode = ADDRESS_MODE_0_PHY;
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63026 )
Change subject: soc/qualcomm/common: verify size of memchipinfo structure
......................................................................
Patch Set 2:
(4 comments)
File src/soc/qualcomm/common/qclib.c:
https://review.coreboot.org/c/coreboot/+/63026/comment/f508812f_0e3c101c
PS1, Line 31: mem_chip_info_size(&memchip)
> Done
Ravi, seriously, _please_ stop answering "Done" to things you didn't actually do! We're losing so much productivity from all the extra review cycles caused by this and the time spent on always having to double-check your comments. Please always make sure you 1. upload the patch, 2. use the diff view to compare your uploaded patch to the previously commented version, and then 3. resolve comments after you have verified that the new patch actually addresses them (you can write comments from right within the diff view, it's very convenient).
https://review.coreboot.org/c/coreboot/+/63026/comment/20b85c84_c9eadd38
PS1, Line 51: sizeof(struct mem_chip_info)
> Done
No you didn't.
https://review.coreboot.org/c/coreboot/+/63026/comment/8a7f6ea3_8b235a1a
PS1, Line 55: memchip
> Done
No you didn't.
https://review.coreboot.org/c/coreboot/+/63026/comment/5f435fcb_093c87aa
PS1, Line 186: mem_chip_addr, sizeof(mem_chip_addr), 0);
> Done
No you didn't.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63144 )
Change subject: src/console/Kconfig: Add option to disable loglevel prefix
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
Patchset:
PS5:
Not sure I really understand the use case here (there's generally no guarantee that coreboot log messages stay the same, so if you have some reader trying to parse them you need to regularly do work to stay up to date anyway)... but if there's demand for it I see no harm in offering the option.
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Change subject: src/arch/arm/include/armv7/arch/cache.h:
......................................................................
Patch Set 1: Code-Review+2
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Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63180 )
Change subject: payloads/tianocore: Don't declare tools directory twice
......................................................................
Set Ready For Review
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Change subject: ec/starlabs/merlin: Add support for Nuvoton EC's
......................................................................
Patch Set 14:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62702/comment/127cc43c_19d2ae98
PS13, Line 12:
> Do you know the EC firmware version/string?
Done
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Hello Felix Singer, build bot (Jenkins), Nico Huber, Michał Żygowski, Tim Wawrzynczak, Michał Kopeć, Paul Menzel, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59548
to look at the new patch set (#19).
Change subject: mb/clevo/tgl-u: add new board L14xMU
......................................................................
mb/clevo/tgl-u: add new board L14xMU
Add new board Clevo L14xMU (TGL).
GPIOs were configured based on schematics.
Tested and working:
- On-board RAM (M471A1G44AB0-CWE)
- DIMM slot (tested Crucial CT16G4SFD8266.16FJ1 / MTA16ATF2G64HZ-2G6J1)
- Graphics (GOP driver), including HDMI
- Keyboard
- I2C touchpad (including interrupt)
- TPM (with interrupt on Windows, only polling on Linux [1])
- microSD Card reader
- both NVME ports
- Speakers
- Microphone
- Camera
- WLAN/BT (CNVi)
- All USB2/3 ports including Type-C
- Thunderbolt detects my work laptop in TB Control Center
(I couldn't test anything more due to security policy.)
- TianoCore
- internal flashing with flashrom on vendor firmware
Note on TPM:
The vendor sets Intel PTT to default-on in newer CSME images, which
conflicts with the dTPM. Currently, there are two ways to make it work:
1) Boot vendor firmware once to let it disable PTT via CSME firmware
feature override.
2) Use Intel Flash Image Tool (FIT) to set "initial power-up state" to
disabled.
Boots fine:
- Debian testing, unstable (Linux 5.16.14, 5.17.0-rc6)
- Windows 10 21H2 (Build 19044.1586)
Untested:
- Thunderbolt (see above)
- Type-C DisplayPort
- S-ATA
Doesn't work:
- TPM interrupt on Linux [1]
- All EC related functions - EC driver is WIP
- WLAN/BT (PCIe) - gets detected but can't be enabled
- 3G/LTE (not powered without EC driver)
- Fn-Keys
- S0ix
- UCSI
- Fan control
- Battery info
[1] https://lkml.org/lkml/2021/5/1/103
Change-Id: I4c4bef3827da10241e9b01e12ecc4276e131a620
Signed-off-by: Michael Niewöhner <foss(a)mniewoehner.de>
---
A src/mainboard/clevo/tgl-u/Kconfig
A src/mainboard/clevo/tgl-u/Kconfig.name
A src/mainboard/clevo/tgl-u/Makefile.inc
A src/mainboard/clevo/tgl-u/board_info.txt
A src/mainboard/clevo/tgl-u/bootblock.c
A src/mainboard/clevo/tgl-u/cmos.default
A src/mainboard/clevo/tgl-u/cmos.layout
A src/mainboard/clevo/tgl-u/dsdt.asl
A src/mainboard/clevo/tgl-u/include/variant/gpio.h
A src/mainboard/clevo/tgl-u/include/variant/ramstage.h
A src/mainboard/clevo/tgl-u/include/variant/romstage.h
A src/mainboard/clevo/tgl-u/ramstage.c
A src/mainboard/clevo/tgl-u/romstage.c
A src/mainboard/clevo/tgl-u/spd/samsung-M471A1G44AB0-CWE.spd.hex
A src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.inc
A src/mainboard/clevo/tgl-u/variants/l140mu/board_info.txt
A src/mainboard/clevo/tgl-u/variants/l140mu/data.vbt
A src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c
A src/mainboard/clevo/tgl-u/variants/l140mu/gpio_early.c
A src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c
A src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c
A src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c
23 files changed, 888 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/59548/19
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63177 )
Change subject: Documentation: gpio: Provide minor fixes to the table
......................................................................
Patch Set 2: Code-Review+2
(1 comment)
Patchset:
PS2:
Thank you!
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