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Change subject: commonlib/timestamp_serialized: Add timestamp enum to name mapping
......................................................................
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Change subject: util/amdfwtool: select A/B recovery when ISH is used
......................................................................
Patch Set 1:
(1 comment)
File util/amdfwtool/amdfwtool.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-144954):
https://review.coreboot.org/c/coreboot/+/63184/comment/5ffbf3e8_676f6a46
PS1, Line 1687: if (cb_config.need_ish) {
braces {} are not necessary for single statement blocks
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Change subject: commonlib/bsd/helpers: Remove redundancy with libpayload defines
......................................................................
Patch Set 5: Code-Review+2
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/helpers.h:
https://review.coreboot.org/c/coreboot/+/62921/comment/c8627d13_2fd426e6
PS5, Line 130: #ifndef STRINGIFY
nit: it would be great if we could get rid of this #ifndef as well, having multiple definition sites is generally not a good pattern. but doesn't need to be in this patch.
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Change subject: mb/amd/chausie/port_descriptors: update DDI descriptors
......................................................................
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Change subject: mb/amd/chausie/devicetree: update PCI root ports
......................................................................
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Change subject: mb/amd/chausie/port_descriptors: update DXIO descriptors
......................................................................
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63122 )
Change subject: soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
......................................................................
soc/amd/sabrina: Do not clear Port80 enable bit in ESPI Decode
This is done to work around a hang when SMU writes to port80. Remove it
after the issue is fixed.
BUG=b:224618411
TEST=Build and boot to OS in Skyrim.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Change-Id: Ic152c295954d33ef1acddb3b06f0c6bbfbfb38ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63122
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/soc/amd/sabrina/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index bef4160..3df7a4b 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -49,6 +49,7 @@
select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_DATA_FABRIC
+ select SOC_AMD_COMMON_BLOCK_ESPI_RETAIN_PORT80_EN # TODO: Remove(b/227201571)
select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_HAS_ESPI # TODO: Check if this is still correct
select SOC_AMD_COMMON_BLOCK_I2C
--
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63186 )
Change subject: util/amdfwtool: use ISH support for Sabrina SoC
......................................................................
util/amdfwtool: use ISH support for Sabrina SoC
The PSP in the Sabrina SoC uses the image slot header to find the second
level PSP directory table, so it needs the ISH to be generated.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I9e6308854147c9f6f72d722215c833ee86ee4f94
---
M util/amdfwtool/amdfwtool.c
1 file changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/63186/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index cdee270..2796cde 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1458,6 +1458,14 @@
}
+static bool needs_ish(enum platform platform_type)
+{
+ if (platform_type == PLATFORM_SABRINA)
+ return true;
+ else
+ return false;
+}
+
int main(int argc, char **argv)
{
int c;
@@ -1689,6 +1697,10 @@
}
}
+ if (needs_ish(soc_id)) {
+ cb_config.need_ish = true;
+ }
+
if (cb_config.need_ish) {
cb_config.recovery_ab = true;
}
--
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Attention is currently required from: Zheng Bao.
Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/63185
to review the following change.
Change subject: util/amdfwtool: add Sabrina SoC type
......................................................................
util/amdfwtool: add Sabrina SoC type
Add PLATFORM_SABRINA to the enum of supported platforms and integrate it
into the existing code.
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ibe52b44395619f697686bd900a522562abbe7646
---
M util/amdfwtool/amdfwtool.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/63185/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index c425676..cdee270 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -558,6 +558,7 @@
PLATFORM_CEZANNE,
PLATFORM_MENDOCINO,
PLATFORM_LUCIENNE,
+ PLATFORM_SABRINA,
};
static uint32_t get_psp_id(enum platform soc_id)
@@ -576,6 +577,7 @@
psp_id = 0xBC0C0140;
break;
case PLATFORM_MENDOCINO:
+ case PLATFORM_SABRINA:
psp_id = 0xBC0D0900;
break;
case PLATFORM_STONEYRIDGE:
@@ -1406,6 +1408,7 @@
case PLATFORM_LUCIENNE:
case PLATFORM_CEZANNE:
case PLATFORM_MENDOCINO:
+ case PLATFORM_SABRINA:
amd_romsig->efs_gen.gen = EFS_SECOND_GEN;
amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode;
amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed;
@@ -1448,6 +1451,8 @@
return PLATFORM_RENOIR;
else if (!strcasecmp(soc_name, "Lucienne"))
return PLATFORM_LUCIENNE;
+ else if (!strcasecmp(soc_name, "Sabrina"))
+ return PLATFORM_SABRINA;
else
return PLATFORM_UNKNOWN;
@@ -1900,6 +1905,7 @@
amd_romsig->bios3_entry = BUFF_TO_RUN(ctx, biosdir);
break;
case PLATFORM_MENDOCINO:
+ case PLATFORM_SABRINA:
break;
case PLATFORM_STONEYRIDGE:
case PLATFORM_RAVEN:
--
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/63184 )
Change subject: util/amdfwtool: select A/B recovery when ISH is used
......................................................................
util/amdfwtool: select A/B recovery when ISH is used
In newer AMD SoCs, the image slot header is used in the AMD A/B recovery
scheme, so set recovery_ab to true when need_ish is true. Also move the
block of code before the process_config call, since that call will
already use the recovery_ab field of the cb_config struct.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I65903765514f215bf5cc9b949d0b95aff781eb34
---
M util/amdfwtool/amdfwtool.c
1 file changed, 8 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/63184/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c
index 9e7f920..c425676 100644
--- a/util/amdfwtool/amdfwtool.c
+++ b/util/amdfwtool/amdfwtool.c
@@ -1684,6 +1684,14 @@
}
}
+ if (cb_config.need_ish) {
+ cb_config.recovery_ab = true;
+ }
+
+ if (cb_config.recovery_ab) {
+ cb_config.multi_level = true;
+ }
+
if (config) {
config_handle = fopen(config, "r");
if (config_handle == NULL) {
@@ -1724,10 +1732,6 @@
retval = 1;
}
- if (cb_config.recovery_ab) {
- cb_config.multi_level = true;
- }
-
if (retval) {
usage();
return retval;
--
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