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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61651/comment/9288ba6b_3cdf6660
PS3, Line 241: void pmc_clear_pmcon_sts(void)
> Well, I still don't see that pain ;) but let's see what others say
>
> ```
> if (PMCON_ON_PCICFG) {
> ...
> } else {
> ...
> }
> ```
You mean, we need another Kconfig to handle this right ?
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Change subject: mb/google/dedede/var/beadrix: Add LTE power off sequence
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
ping coreboot owner to help review. thanks!
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Change subject: mb/google/dedede/var/beadrix: Add LTE modem support
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Patchset:
PS1:
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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61651/comment/6b56f3e7_cc8d4732
PS3, Line 241: void pmc_clear_pmcon_sts(void)
> > copypastacopypasta see https://review.coreboot. […]
Well, I still don't see that pain ;) but let's see what others say
```
if (PMCON_ON_PCICFG) {
...
} else {
...
}
```
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61850
to look at the new patch set (#2).
Change subject: sb/intel/lynxpoint/hda_verb.c: Read 16 bits on HDA_STATESTS_REG
......................................................................
sb/intel/lynxpoint/hda_verb.c: Read 16 bits on HDA_STATESTS_REG
HDA_STATESTS_REG is a 16 bits register, so correct the codec_mask
and read 16bits.
Change-Id: Ia82ca04dac25efba1a173a690da75e8b3063b147
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/southbridge/intel/lynxpoint/azalia.c
M src/southbridge/intel/lynxpoint/hda_verb.c
M src/southbridge/intel/lynxpoint/hda_verb.h
3 files changed, 12 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61850/2
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61849
to look at the new patch set (#2).
Change subject: soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
---
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
1 file changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61849/2
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