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Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(2 comments)
File src/soc/intel/xeon_sp/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61652/comment/aba63696_9bd847da
PS3, Line 183: void pmc_clear_pmcon_sts(void)
> copypastacopypasta see https://review.coreboot. […]
Ack
https://review.coreboot.org/c/coreboot/+/61652/comment/36d6f01d_c6db8136
PS3, Line 187: addr = pmc_mmio_regs();
:
: reg_val = read32(addr + GEN_PMCON_A);
:
> > PCICFG […]
Ack
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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
soc/intel/apollolake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I982f669b13f25d1d0e6dfaec2fbf50d3200f74fe
---
M src/soc/intel/apollolake/include/soc/pm.h
M src/soc/intel/apollolake/pmutil.c
2 files changed, 17 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/61651/4
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Change subject: soc/intel/xeon_sp: Add function to clear PMCON status bits
......................................................................
soc/intel/xeon_sp: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I22650f539a1646f93f2c6494cbf54b8ca785d6ad
---
M src/soc/intel/xeon_sp/include/soc/pm.h
M src/soc/intel/xeon_sp/include/soc/pmc.h
M src/soc/intel/xeon_sp/pmutil.c
3 files changed, 19 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/61652/4
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Change subject: sb/intel/i82801gx/azalia.c: Fix read on 16bits register
......................................................................
sb/intel/i82801gx/azalia.c: Fix read on 16bits register
Regarding I/O Controller Hub 7 datasheet (page #735), STATESTS is a
16 bits register. So correct the codec mask and read only 16 bits.
Change-Id: I530aa21d5a26ade0bc071351ac609c84bd8eb2cb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/southbridge/intel/i82801gx/azalia.c
1 file changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/61845/2
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Change subject: soc/intel/apollolake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/apollolake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61651/comment/08f8b030_5bc28352
PS3, Line 241: void pmc_clear_pmcon_sts(void)
> copypastacopypasta see https://review.coreboot.org/c/coreboot/+/61650/3/src/soc/intel/skylake/pmut…
I hope we can now keep this implementation inside SoC knowing the PMCON can resides inside PCI config or PCI MMIO in different SoC platform, so, it might create pain to make it common code.
Please reopen if you think otherwise.
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
Patch Set 3:
(4 comments)
File src/soc/intel/skylake/pmc.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/3e8f204b_2bdc6000
PS3, Line 99: pci_or_config32(dev, GEN_PMCON_A, 0);
> Understood, then this one should be dropped
Ack
File src/soc/intel/skylake/pmutil.c:
https://review.coreboot.org/c/coreboot/+/61650/comment/ce711493_9bef71ae
PS3, Line 269: void pmc_clear_pmcon_sts(void)
> > > > > > > this function is all the same for all platforms using common code, so why exactly do we […]
Ack
https://review.coreboot.org/c/coreboot/+/61650/comment/bc0a90b5_1c99e7ed
PS3, Line 273: addr = pmc_mmio_regs();
:
: reg_val = read32(addr + GEN_PMCON_A);
> Oops :(
Ack
https://review.coreboot.org/c/coreboot/+/61650/comment/6d2c7814_1e042146
PS3, Line 276: /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits
: * while retaining MS4V write-1-to-clear bit
> nit: not a valid comment according to coreboot codestyle docs ;)
Ack
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Change subject: soc/intel/skylake: Add function to clear PMCON status bits
......................................................................
soc/intel/skylake: Add function to clear PMCON status bits
This patch adds an SoC function to clear GEN_PMCON_A status bits to
align with other IA coreboot implementations.
Additionally, move the PMCON status bit clear operation to finalize.c
to cover any such chances where FSP-S NotifyPhase requested a global
reset and PMCON status bit remains set.
BUG=b:211954778
TEST=None.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Ie786e6ba2daf88accb5d70be33de0abe593f8c53
---
M src/soc/intel/skylake/finalize.c
M src/soc/intel/skylake/include/soc/pm.h
M src/soc/intel/skylake/pmc.c
M src/soc/intel/skylake/pmutil.c
4 files changed, 20 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/61650/4
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Change subject: mb/google/guybrush: Add a mainboard specific SPL table
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS1:
> Seems OK to me. […]
I tried and I can upload to blobs.
But it seems that we still need to discuss if it is allowed.
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Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/blobs/+/61844
to review the following change.
Change subject: mb/google/guybrush: Add SPL table
......................................................................
mb/google/guybrush: Add SPL table
Change-Id: I651bc76ca8f71ea842ca9ddb4ba99cfe03fc31bb
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M mainboard/google/guybrush/Release.txt
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/blobs refs/changes/44/61844/1
diff --git a/mainboard/google/guybrush/Release.txt b/mainboard/google/guybrush/Release.txt
index f5cb48b..df803b8 100644
--- a/mainboard/google/guybrush/Release.txt
+++ b/mainboard/google/guybrush/Release.txt
@@ -1,4 +1,7 @@
Files:
+ TypeId0x55_SplTable_Prod_CZN_Chrome.sbin - SPL for Guybrush
+
+Files:
APCB_CZN_D4.bin - Data only - No license, ABI or Version #
2021-04-05:
--
To view, visit https://review.coreboot.org/c/blobs/+/61844
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Gerrit-Project: blobs
Gerrit-Branch: master
Gerrit-Change-Id: I651bc76ca8f71ea842ca9ddb4ba99cfe03fc31bb
Gerrit-Change-Number: 61844
Gerrit-PatchSet: 1
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Zheng Bao
Gerrit-Attention: Zheng Bao
Gerrit-MessageType: newchange