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Change subject: soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
Patch Set 1:
(3 comments)
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140568):
https://review.coreboot.org/c/coreboot/+/61849/comment/502bf913_07cb2eae
PS1, Line 156: printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior operation" \
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140568):
https://review.coreboot.org/c/coreboot/+/61849/comment/4c678814_0dc9bcbe
PS1, Line 156: printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior operation" \
Avoid unnecessary line continuations
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-140568):
https://review.coreboot.org/c/coreboot/+/61849/comment/711855d9_485c6534
PS1, Line 157: " at Flash Offset %x\n", SPIBAR_HWSEQ_XFER_TIMEOUT_MS, flash_addr);
line over 96 characters
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Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61849 )
Change subject: soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
......................................................................
soc/intel/fast_spi: Check SPI Cycle In-Progress prior start HW Seq
As per EDS, SPI controller sets the HSFSTS.bit5 (SCIP) when software
sets the Flash Cycle Go (FGO) bit in the Hardware Sequencing Flash
Control register.
This bit remains set until the cycle completes on the SPI interface.
Hardware automatically sets and clears this bit so that software can
determine when read data is valid and/or when it is safe to begin
programming the next command.
Software must initiate the next SPI transaction when this bit is 0.
Added non-blocking mechanism with `5sec` timeout to report back error
if current SPI transaction is failing due to on-going SPI access.
BUG=b:215255210
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I4d35058244a73e77f6204c4d04d09bae9e5ac62c
---
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/61849/1
diff --git a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
index aead8de..a789077 100644
--- a/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
+++ b/src/soc/intel/common/block/fast_spi/fast_spi_flash.c
@@ -129,11 +129,35 @@
return E_TIMEOUT;
}
+static int wait_for_hwseq_spi_cycle_complete(struct fast_spi_flash_ctx *ctx)
+{
+ struct stopwatch sw;
+ uint32_t hsfsts;
+
+ stopwatch_init_msecs_expire(&sw, SPIBAR_HWSEQ_XFER_TIMEOUT_MS);
+ do {
+ hsfsts = fast_spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL);
+
+ if (hsfsts & SPIBAR_HSFSTS_SCIP)
+ printk(BIOS_INFO, "SPI Transaction in progress..\n");
+ else
+ return SUCCESS;
+ } while (!(stopwatch_expired(&sw)));
+
+ return E_TIMEOUT;
+}
+
/* Execute FAST_SPI flash transfer. This is a blocking call. */
static int exec_sync_hwseq_xfer(struct fast_spi_flash_ctx *ctx,
uint32_t hsfsts_cycle, uint32_t flash_addr,
size_t len)
{
+ if (wait_for_hwseq_spi_cycle_complete(ctx) != SUCCESS) {
+ printk(BIOS_ERR, "SPI Transaction Timeout (Exceeded %d ms) due to prior operation" \
+ " at Flash Offset %x\n", SPIBAR_HWSEQ_XFER_TIMEOUT_MS, flash_addr);
+ return E_TIMEOUT;
+ }
+
start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len);
return wait_for_hwseq_xfer(ctx, flash_addr);
}
--
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61776 )
Change subject: Revert "cpu/x86/lapic: Unconditionally use CPUID leaf 0xb if available"
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61776/comment/f843ed4c_7e8054a0
PS1, Line 16: valid APIC ID.
> the cezanne ppr #56569 rev 3.03 has the following definition […]
My expectation had been that AMD implements the standard CPUID set in compliance with IA32 / X86_64 manual. Obviously this assumption is wrong. Bit 21 of ECX (not EAX) CPUID leaf 1 should work, while documented as reserved in #25481.
So the later #55570 rev 3.16 documents leaf 0xb as implemented, while the PCO hardware behaved like earlier rev 3.14? Are the top EDX 24 bits really reserved or zero?
Platforms supporting X2APIC probably should never use XAPIC_ONLY=y. With intel, bottom LAPIC ID bits may have a shift, so the 8 bits of CPUID leaf 0x1 EDX may be insufficient already with MAX_CPUS < 256.
Payloads may need to be modified for X2APIC mode.
From IA32/64 SDM
10.12.2 x2APIC Register Availability
In x2APIC mode, the memory mapped interface is not available and any access
to the MMIO interface will behave similar to that of a legacy xAPIC in globally
disabled state.
I have also seen kernel messages like this:
Switched APIC routing to cluster x2apic.
So SMM may see LAPICs in x2apic mode even with coreboot proper built with XAPIC_ONLY.
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Hello Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61846
to look at the new patch set (#2).
Change subject: sb/intel/bd82x6x/azalia.c: Read 16 bits on HDA_STATESTS_REG
......................................................................
sb/intel/bd82x6x/azalia.c: Read 16 bits on HDA_STATESTS_REG
HDA_STATESTS_REG is a 16 bits register, so correct the codec_mask
and read 16bits.
Change-Id: I5d879462bbc390aa85c75e18d124175da5e34adb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/southbridge/intel/bd82x6x/azalia.c
1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/61846/2
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Robert Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61847 )
Change subject: mb/google/brya/vell: Add 5G WWAN ACPI support for vell
......................................................................
mb/google/brya/vell: Add 5G WWAN ACPI support for vell
Add FM350GL 5G WWAN support using drivers/wwan/fm and addtional PM
features from RTD3.
Change-Id: If6d3f965b8f6b6753446f55a8bd47d3b0c1ae7be
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/vell/gpio.c
M src/mainboard/google/brya/variants/vell/overridetree.cb
2 files changed, 21 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/61847/1
diff --git a/src/mainboard/google/brya/variants/vell/gpio.c b/src/mainboard/google/brya/variants/vell/gpio.c
index 6dbfb69..ac102bd 100644
--- a/src/mainboard/google/brya/variants/vell/gpio.c
+++ b/src/mainboard/google/brya/variants/vell/gpio.c
@@ -90,6 +90,12 @@
/* GPD11: LANPHYC ==> WWAN_CONFIG1 */
PAD_NC(GPD11, NONE),
+
+ /* E0 : SATAXPCIE0 ==> WWAN_PERST_L
+ NB. Driven high here so that it is sequenced after WWAN_RST_L; a
+ PERST# signal would normally be reset by PLRST#, but here it will be
+ explicitly programmed during a power-down sequence. */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP),
};
/* Early pad configuration in bootblock */
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 4daf446..55779ce 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -14,7 +14,7 @@
end
field DB_LTE 6 7
option LTE_ABSENT 0
- option LTE_USB 1
+ option LTE_PCIE 1
end
field EPS 10 10
option PRIVACY_SCREEN_ABSENT 0
@@ -154,6 +154,20 @@
device generic 0 on end
end
end
+ device ref pcie_rp6 on
+ probe DB_LTE LTE_PCIE
+ chip drivers/wwan/fm
+ register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
+ register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)"
+ register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E0)"
+ register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A7)"
+ use rp6_rtd3 as rtd3dev
+ device generic 0 on
+ probe DB_LTE LTE_PCIE
+ end
+ end
+ end
+
device ref pcie_rp8 off end
device ref pcie_rp9 off end
device ref tcss_dma0 on
--
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Hello build bot (Jenkins), Tim Wawrzynczak,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61780
to look at the new patch set (#2).
Change subject: mb/google/brya/var/vell: Add Wifi SAR for vell
......................................................................
mb/google/brya/var/vell: Add Wifi SAR for vell
Add wifi sar for vell
BUG=b:
TEST=emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
Change-Id: I9797069d9d050bdae9e819c72c80179fa468a6f7
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig.name
M src/mainboard/google/brya/variants/vell/Makefile.inc
A src/mainboard/google/brya/variants/vell/variant.c
3 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/61780/2
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Change subject: sb/intel/i82801gx/azalia.c: Fix read on 16bits register
......................................................................
sb/intel/i82801gx/azalia.c: Fix read on 16bits register
Regarding I/O Controller Hub 7 datasheet (page #735), STATESTS is a
16 bits register. So correct the codec mask and read only 16 bits.
Change-Id: I530aa21d5a26ade0bc071351ac609c84bd8eb2cb
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/southbridge/intel/i82801gx/azalia.c
1 file changed, 8 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/61845/3
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61649 )
Change subject: soc/intel/*/pmc: Add `finalize` operation for pmc
......................................................................
Patch Set 8:
(1 comment)
File src/soc/intel/cannonlake/pmc.c:
https://review.coreboot.org/c/coreboot/+/61649/comment/e51bde04_061f61ed
PS8, Line 146: pmc_clear_pmcon_sts();
> this probably should be done in soc_pmc_init instead of finalize. […]
I have provided the clarification why we need this at later stage. Please reopen if you think otherwise.
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