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Change subject: mb/google/guybrush: Add a mainboard specific SPL table
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61838/comment/be357933_89aba83c
PS2, Line 8:
Why can’t the generic one be used?
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Change subject: soc/amd/cezanne: Add options to Kconfig to give a SPL table
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Patch Set 2: Code-Review+1
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Change subject: amdfwtool: Add options to support mainboard specific SPL table
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Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61836/comment/def77380_874986df
PS2, Line 10: ChromeBook
Chromebook
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Change subject: drivers/smmstore/store.c: Fix static assertion for memory mapped SOCs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> > They're one and the same (for IFWI at least). […]
If the address is aligned in FMAP, then it won't be aligned when its memory-mapped and problems ensue.
APL and GLK will memory map the BIOS region (BP1 + BP2) at (0x100000000 - sizeof(BIOS)). And NvStorage has to be the last section.
An example, using this:
https://review.coreboot.org/c/coreboot/+/60980/49/src/mainboard/starlabs/li…
If you align SMMStore in FMAP at 0x690000, it will be memory mapped at 0xFFF41000 and doesn't work.
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Change subject: drivers/smmstore/store.c: Fix static assertion for memory mapped SOCs
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Patch Set 1:
(1 comment)
Patchset:
PS1:
> They're one and the same (for IFWI at least).
I'm not sure what you mean. The address in flash should be aligned and that is what is represented in FMAP.
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Change subject: drivers/smmstore/store.c: Fix static assertion for memory mapped SOCs
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Patch Set 1:
(1 comment)
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PS1:
> It's not really about how they are memory mapped but how it's in flash.
They're one and the same (for IFWI at least).
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Change subject: drivers/smmstore/store.c: Fix static assertion for memory mapped SOCs
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
It's not really about how they are memory mapped but how it's in flash.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device
......................................................................
mb/google/guybrush/var/nipperkin: Add _HID for privacy screen device
BUG=b:204401306
BRANCH=guybrush
TEST=emerge-guybrush coreboot
dump SSDT, see _HID instead of _ADR
Change-Id: I3f45fabac1548cca39379f91cc42fed0cd04f8a3
Signed-off-by: Kevin Chiu <kevin.chiu.17802(a)gmail.com>
---
M src/mainboard/google/guybrush/Kconfig.name
M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
2 files changed, 14 insertions(+), 0 deletions(-)
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Change subject: soc/amd/common: Scan bridge devices behind SoCs GPU Controller
......................................................................
soc/amd/common: Scan bridge devices behind SoCs GPU Controller
Scan devices behind SoCs GPU controller to expose more buses.
BUG=b:204401306
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