coreboot-gerrit December 2022

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: tests: Ignore RWX segment warning
by Jakub Czapiga (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Elyes Haouas. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70252 ) Change subject: tests: Ignore RWX segment warning ...................................................................... Patch Set 2: (1 comment) File tests/Makefile.common: https://review.coreboot.org/c/coreboot/+/70252/comment/8d6682c8_088d632b PS2, Line 69: TEST_LDFLAGS += --no-warn-rwx-segments Can you elaborate on why this is needed? I do not see where it would be useful right now, and we do not want to execute sections other than .text -- To view, visit https://review.coreboot.org/c/coreboot/+/70252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I593eea3bcac8e9e46883b73b25a31e20b4c27c51 Gerrit-Change-Number: 70252 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 02 Dec 2022 08:03:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/intel/mtlrvp: Add MTL-P RVP board ids
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Wonkyu Kim, Ravishankar Sarawadi, Rizwan Qureshi, Angel Pons, Krishna P Bhat D, Tim Wawrzynczak, Tarun Tuli, Jamie Ryu, Harsha B R, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Raj Astekar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66102 ) Change subject: mb/intel/mtlrvp: Add MTL-P RVP board ids ...................................................................... Patch Set 15: (1 comment) Patchset: PS15: I thought u have a common implementation now ? -- To view, visit https://review.coreboot.org/c/coreboot/+/66102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90b0543d5db208f696d2c2c2dc3d2581514a845b Gerrit-Change-Number: 66102 Gerrit-PatchSet: 15 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 08:01:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: soc/intel/common, alderlake: provide a list of D-states to enter LPM
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Tarun Tuli, Eran Mitrani, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70166 ) Change subject: soc/intel/common, alderlake: provide a list of D-states to enter LPM ...................................................................... Patch Set 7: Code-Review+1 (6 comments) File src/soc/intel/alderlake/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/076610c8_6799d2e4 PS7, Line 168: struct min_sleep_state min_pci_sleep_states[] = { how about marking this structure as static ? https://review.coreboot.org/c/coreboot/+/70166/comment/b711f7f1_95a15dbc PS7, Line 233: soc_lpi_get_constraints can't we call `acpi_generate_lpi_constraint_table()` directly from pep.c file ? File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70166/comment/55e0283f_4fe67196 PS7, Line 30: = 0 same https://review.coreboot.org/c/coreboot/+/70166/comment/5132542d_ad2249e2 PS7, Line 31: }; please one blank line https://review.coreboot.org/c/coreboot/+/70166/comment/5de0b548_a9713666 PS7, Line 33: LPI_DISANBLED = 0, : LPI_ENABLED = 1, nit: you can avoid assignments. https://review.coreboot.org/c/coreboot/+/70166/comment/aeed0873_01d8075f PS7, Line 455: ar `ar` is like array ? if yes, then u can use `arr` -- To view, visit https://review.coreboot.org/c/coreboot/+/70166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I45eded3868a4987cb5eb0676c50378ac52ec3752 Gerrit-Change-Number: 70166 Gerrit-PatchSet: 7 Gerrit-Owner: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 08:00:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: coreboot_tables: Make existing alignment conventions more explicit
by Jakub Czapiga (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Peter Stuge, Julius Werner, Martin Roth, ron minnich. Jakub Czapiga has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70158 ) Change subject: coreboot_tables: Make existing alignment conventions more explicit ...................................................................... Patch Set 2: (2 comments) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/70158/comment/60fc59f9_f97de2f0 PS2, Line 209: uint8_t pad[2]; : }; : Will padding work without structure packing? File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/70158/comment/1c8c2501_b2bcc22b PS2, Line 80: assert(IS_ALIGNED(rec->size, LB_ENTRY_ALIGN)); Without packing on proper size alignment it will fail very often. Many entries do not have their size aligned properly. -- To view, visit https://review.coreboot.org/c/coreboot/+/70158 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeef29ef255047a855066469e03b5481812e5975 Gerrit-Change-Number: 70158 Gerrit-PatchSet: 2 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Peter Stuge <peter(a)stuge.se> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Peter Stuge <peter(a)stuge.se> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 07:55:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate
by Elyes Haouas (Code Review) 02 Dec '22

02 Dec '22

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70255 ) Change subject: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate ...................................................................... superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate Change-Id: Idb321302bc82eb1b73bc1e732b82b9f726d2f363 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb M src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb M src/superio/nuvoton/nct5104d/chip.h M src/superio/nuvoton/nct5104d/superio.c 6 files changed, 23 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/70255/1 diff --git a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb index 243a9ba..5e330f3 100644 --- a/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu2/devicetree.cb @@ -32,8 +32,8 @@ device pci 14.0 on end # SM device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - register "reset_gpios" = "1" + register "irq_trigger_type" = "false" + register "reset_gpios" = "true" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 8273a96..932eb8e 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -32,8 +32,8 @@ device pci 14.0 on end # SM device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - register "reset_gpios" = "1" + register "irq_trigger_type" = "false" + register "reset_gpios" = "true" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index f399d8b..59b1b79 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -32,8 +32,8 @@ device pci 14.0 on end # SM device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" - register "reset_gpios" = "1" + register "irq_trigger_type" = "false" + register "reset_gpios" = "true" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb index c69401b..a08cf0d 100644 --- a/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu5/devicetree.cb @@ -32,7 +32,7 @@ device pci 14.0 on end # SM device pci 14.3 on # LPC 0x439d chip superio/nuvoton/nct5104d # SIO NCT5104D - register "irq_trigger_type" = "0" + register "irq_trigger_type" = "false" device pnp 2e.0 off end device pnp 2e.2 on io 0x60 = 0x3f8 diff --git a/src/superio/nuvoton/nct5104d/chip.h b/src/superio/nuvoton/nct5104d/chip.h index a251aa5..2e2ca42 100644 --- a/src/superio/nuvoton/nct5104d/chip.h +++ b/src/superio/nuvoton/nct5104d/chip.h @@ -3,9 +3,11 @@ #ifndef SUPERIO_NUVOTON_NCT5104D_CHIP_H #define SUPERIO_NUVOTON_NCT5104D_CHIP_H +#include <stdbool.h> + struct superio_nuvoton_nct5104d_config { - u8 irq_trigger_type; - u8 reset_gpios; + bool irq_trigger_type; + bool reset_gpios; }; #endif diff --git a/src/superio/nuvoton/nct5104d/superio.c b/src/superio/nuvoton/nct5104d/superio.c index cfa2228..fea4b57 100644 --- a/src/superio/nuvoton/nct5104d/superio.c +++ b/src/superio/nuvoton/nct5104d/superio.c @@ -173,12 +173,12 @@ switch (dev->path.pnp.device) { case NCT5104D_SP1: case NCT5104D_SP2: - set_irq_trigger_type(dev, conf->irq_trigger_type != 0); + set_irq_trigger_type(dev, conf->irq_trigger_type != false); break; case NCT5104D_SP3: case NCT5104D_SP4: route_pins_to_uart(dev, true); - set_irq_trigger_type(dev, conf->irq_trigger_type != 0); + set_irq_trigger_type(dev, conf->irq_trigger_type != false); break; case NCT5104D_GPIO0: case NCT5104D_GPIO1: -- To view, visit https://review.coreboot.org/c/coreboot/+/70255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb321302bc82eb1b73bc1e732b82b9f726d2f363 Gerrit-Change-Number: 70255 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel: Adopt new common/pmbase
by build bot (Jenkins) (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jeff Daly, Sean Rhodes, Vanessa Eusebio, Kyösti Mälkki. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70050 ) Change subject: soc/intel: Adopt new common/pmbase ...................................................................... Patch Set 6: (1 comment) File src/southbridge/intel/common/pmbase.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-165057): https://review.coreboot.org/c/coreboot/+/70050/comment/09156602_5298c7dd PS6, Line 11: CONFIG(SOC_INTEL_BROADWELL) || CONFIG(SOC_INTEL_DENVERTON_NS) please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/70050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Gerrit-Change-Number: 70050 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 07:53:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel: Adopt new common/pmbase
by Kyösti Mälkki (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jeff Daly, Sean Rhodes, Vanessa Eusebio, Kyösti Mälkki. Hello build bot (Jenkins), Jeff Daly, Sean Rhodes, Vanessa Eusebio, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70050 to look at the new patch set (#6). Change subject: soc/intel: Adopt new common/pmbase ...................................................................... soc/intel: Adopt new common/pmbase Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/acer/aspire_vn7_572g/mainboard.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/common/block/pmc/pmclib.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/block/smm/smitraphandler.c M src/soc/intel/denverton_ns/pmutil.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/smm.c M src/soc/intel/skylake/pmc.c M src/southbridge/intel/common/pmbase.h 10 files changed, 55 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/70050/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/70050 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I473ebefcf8e0c929f6cbf6b5c0d7e8f5af72856d Gerrit-Change-Number: 70050 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/meteorlake: Allow sending late EOP cmd to CSE
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69999 ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/meteorlake: Allow sending late EOP cmd to CSE ...................................................................... soc/intel/meteorlake: Allow sending late EOP cmd to CSE This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA common code to skip sending CSE EOP cmd during finalize operation rather uses boot state machine (either payload load or payload boot) to delay in sending EOP cmd to CSE. BUG=b:260041679 TEST=Able to boot to Google/Rex with this patch and observed ~150ms savings in boot time Without this patch: 942:before sending EOP to ME 1,795,702 (354) 943:after sending EOP to ME 1,950,526 (154,824) With this patch: 942:before sending EOP to ME 2,051,406 (35,484) 943:after sending EOP to ME 2,057,583 (6,177) Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999 Reviewed-by: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/meteorlake/Kconfig 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Ivy Jian: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index c3efd3e..fb99d30 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -82,6 +82,7 @@ select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_IOC + select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION -- To view, visit https://review.coreboot.org/c/coreboot/+/69999 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d Gerrit-Change-Number: 69999 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69978 ) Change subject: soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP ...................................................................... soc/intel/cmn/cse: Allow to perform essential CSE operations post EOP This patch allows to send late EOP cmd to CSE (after CSE .final) using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD) if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config. Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()` to make the function name more meaningful with its operation. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/common/block/cse/cse_eop.c 1 file changed, 30 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index b8b8e36..53a4fa5 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -238,9 +238,11 @@ return do_send_end_of_post(); } -static void set_cse_end_of_post(void *unused) +static void send_cse_eop_with_late_finalize(void *unused) { - return do_send_end_of_post(); + do_send_end_of_post(); + if (CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + cse_late_finalize(); } /* @@ -253,7 +255,7 @@ * BS_PAYLOAD_BOOT instead. */ #if !CONFIG(HECI_DISABLE_USING_SMM) -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, set_cse_end_of_post, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, send_cse_eop_with_late_finalize, NULL); #else -BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, set_cse_end_of_post, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, send_cse_eop_with_late_finalize, NULL); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/69978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c Gerrit-Change-Number: 69978 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/cmn/cse: API to perform essential CSE operations post EOP
by Subrata Banik (Code Review) 02 Dec '22

02 Dec '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69977 ) ( 5 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/cmn/cse: API to perform essential CSE operations post EOP ...................................................................... soc/intel/cmn/cse: API to perform essential CSE operations post EOP This patch creates an API that can perform essential CSE operation after sending the late EOP command to the CSE and prior booting to OS. Lists of operation are - Perform global reset lock - Put HECI1 to D0i3 and disable the HECI1 if the user selects - Set D0I3 for all HECI devices. BUG=b:260041679 TEST=Able to boot Google/Rex after sending CSE EOP late. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 47 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 9b8db54..8f32c7c 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1256,6 +1256,22 @@ } /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void) +{ + if (!CONFIG(SOC_INTEL_CSE_SEND_EOP_LATE)) + return; + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT)) + cse_final_ready_to_boot(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) + cse_final_end_of_firmware(); +} + +/* * `cse_final` function is native implementation of equivalent events performed by * each FSP NotifyPhase() API invocations. */ diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index cceee4f..bccdc4e 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -542,6 +542,12 @@ void cse_send_end_of_post(void); /* + * This function to perform essential post EOP cse related operations + * upon SoC selecting `SOC_INTEL_CSE_SEND_EOP_LATE` config + */ +void cse_late_finalize(void); + +/* * SoC override API to make heci1 disable using PCR. * * Allow SoC to implement heci1 disable override due to PSF registers being -- To view, visit https://review.coreboot.org/c/coreboot/+/69977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563 Gerrit-Change-Number: 69977 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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