coreboot-gerrit December 2022

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[S] Change in coreboot[master]: acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Lance Zhao, Tim Wawrzynczak, Kyösti Mälkki. Hello Lance Zhao, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70267 to look at the new patch set (#3). Change subject: acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw ...................................................................... acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw This reads back the ioapic id from hardware. Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/70267/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3 Gerrit-Change-Number: 70267 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu. Hello Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70265 to look at the new patch set (#5). Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... soc/intel/xeon_sp: Read ioapic configuration from hardware This is more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 37 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70265 ) Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... Patch Set 3: (2 comments) File src/soc/intel/common/block/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/70265/comment/c769dce8_0a31a0e6 PS1, Line 96: current += acpi_create_madt_ioapic_from_hw((void *)current, ioapic_table[i]); > Currently GSIs are assigned in the order these calls are made. There are some assumptions that GSIs 0-15 are connected to legacy IRQs, so the first IOAPIC on the table needs to be the one delivering superio SERIRQs, i8254(?) timer etc. > > Could already be the case, I did not dig into soc_get_ioapic_info() and the HOBs to say. That is currently true. The first IOAPIC reported is the PCH one which has the 0-15 GSI. File src/soc/intel/xeon_sp/acpi.c: https://review.coreboot.org/c/coreboot/+/70265/comment/11043f2a_1df6fda8 PS1, Line 99: xeonsp_ioapic_bases[index++] = hob->PlatformData.IIO_resource[0].StackRes[0].IoApicBase; > With XEON_SP_HAVE_IIO_IOAPIC=y, does this get added again at index 1, and emit associated MADT entries twice? > > I have no clue what is_iio_stack_res() checks. iio_stack_res are the resources on a PCI root bridge that Intel call IIO stack. I forgot: if (stack == 0 && socket == 0) madt_tbl[cur_index].addr += 0x1000; -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:41:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Read ioapic configuration from hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Hello Jonathan Zhang, Johnny Lin, Christian Walter, Kyösti Mälkki, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70265 to look at the new patch set (#4). Change subject: soc/intel/xeon_sp: Read ioapic configuration from hardware ...................................................................... soc/intel/xeon_sp: Read ioapic configuration from hardware This more robust than hardcoding whathever FSP has set up and is a lot less code. Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/acpi/acpi.c M src/soc/intel/common/block/include/intelblocks/acpi.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/skx/Kconfig 5 files changed, 37 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/70265/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/70265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6423ddc139d742879d791b054ea082768749c0a7 Gerrit-Change-Number: 70265 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: amdfwtool: Add the new entry type for new family morgana
by ritul guru (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Bao Zheng, Jason Glenesk, Marshall Dawson, Zheng Bao, Martin Roth. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69045 ) Change subject: amdfwtool: Add the new entry type for new family morgana ...................................................................... Patch Set 9: (2 comments) File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/69045/comment/c8478fa7_db02f095 PS9, Line 281: else if (strcmp(fw_name, "RIB_FILE") == 0) { : fw_type = AMD_RIB; : subprog = 0; : } can we add two subprogram 1 as well for RIB? https://review.coreboot.org/c/coreboot/+/69045/comment/c26e2166_1b895b30 PS9, Line 371: TPMLITE_FILE is it applicable for HSP FW as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/69045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Gerrit-Change-Number: 69045 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 12:39:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jonathan Zhang, Johnny Lin, Christian Walter, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70270 ) Change subject: soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW ...................................................................... soc/intel/xeon_sp: Add DMAR IOAPIC entries based on HW Instead of guessing how FSP has set up IOAPIC IDs read it back from hardware. This is more robust. Change-Id: If90873ac94261e424d1713bdab137eaceb256bba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/nb_acpi.c M src/soc/intel/xeon_sp/skx/soc_util.c 4 files changed, 22 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/70270/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index cd1e06d..0853292 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -61,24 +61,3 @@ else return -1; } - -uint8_t soc_get_iio_ioapicid(int socket, int stack) -{ - uint8_t ioapic_id = socket ? 0xf : 0x9; - switch (stack) { - case CSTACK: - break; - case PSTACK0: - ioapic_id += 1; - break; - case PSTACK1: - ioapic_id += 2; - break; - case PSTACK2: - ioapic_id += 3; - break; - default: - return 0xff; - } - return ioapic_id; -} diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 213735a..7435d01 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -14,7 +14,6 @@ unsigned int soc_get_num_cpus(void); void xeonsp_init_cpu_config(void); void set_bios_init_completion(void); -uint8_t soc_get_iio_ioapicid(int socket, int stack); struct iiostack_resource { uint8_t no_of_stacks; diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/nb_acpi.c index 42b52f3..6b8396d 100644 --- a/src/soc/intel/xeon_sp/nb_acpi.c +++ b/src/soc/intel/xeon_sp/nb_acpi.c @@ -14,6 +14,7 @@ #include <soc/soc_util.h> #include <soc/util.h> #include <intelblocks/p2sb.h> +#include <stdint.h> #include "chip.h" @@ -182,13 +183,13 @@ static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack, const IIO_UDS *hob) { - uint32_t enum_id; unsigned long tmp = current; uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; uint32_t reg_base = hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + uint32_t ioapic_base = hob->PlatformData.IIO_resource[socket].StackRes[stack].IoApicBase; printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", __func__, socket, stack, bus, pcie_seg, reg_base); @@ -212,18 +213,19 @@ // Add PCH IOAPIC if (socket == 0 && stack == CSTACK) { union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + printk(BIOS_DEBUG, " [IOAPIC Device] Base: 0x%x, PCI Bus Number: 0x%x, " "PCI Path: 0x%x, 0x%x\n", PCH_IOAPIC_ID, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); - current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + current += acpi_create_dmar_ds_ioapic_from_hw(current, ioapic_base, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); } // Add IOAPIC entry - enum_id = soc_get_iio_ioapicid(socket, stack); - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + if (socket == 0 && stack == CSTACK) + ioapic_base += 0x1000; + printk(BIOS_DEBUG, " [IOAPIC Device] Base: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", ioapic_base, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic_from_hw(current, ioapic_base, bus, APIC_DEV_NUM, APIC_FUNC_NUM); // Add CBDMA devices for CSTACK diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 3258007..7e71914 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -148,24 +148,3 @@ else return -1; } - -uint8_t soc_get_iio_ioapicid(int socket, int stack) -{ - uint8_t ioapic_id = socket ? 0xf : 0x9; - switch (stack) { - case CSTACK: - break; - case PSTACK0: - ioapic_id += 1; - break; - case PSTACK1: - ioapic_id += 2; - break; - case PSTACK2: - ioapic_id += 3; - break; - default: - return 0xff; - } - return ioapic_id; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/70270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If90873ac94261e424d1713bdab137eaceb256bba Gerrit-Change-Number: 70270 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: nb/intel: Set DMAR IOAPIC entry based on hardware
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Angel Pons. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70269 ) Change subject: nb/intel: Set DMAR IOAPIC entry based on hardware ...................................................................... nb/intel: Set DMAR IOAPIC entry based on hardware This avoids the need to hardcode the IOAPIC id. Change-Id: Iccc9387734fd39e7ffe504c65d2441b580130eab Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c 2 files changed, 16 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/70269/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 290dc1e..30977085 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" @@ -38,7 +39,7 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c2f6eae..ff180e0 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "sandybridge.h" @@ -42,7 +43,7 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; -- To view, visit https://review.coreboot.org/c/coreboot/+/70269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccc9387734fd39e7ffe504c65d2441b580130eab Gerrit-Change-Number: 70269 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel: Set IO APIC DMAR entry based on hw
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Jeff Daly, Sean Rhodes, Tarun Tuli, Subrata Banik, Kapil Porwal, Vanessa Eusebio, Lean Sheng Tan, Werner Zeh. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70268 ) Change subject: soc/intel: Set IO APIC DMAR entry based on hw ...................................................................... soc/intel: Set IO APIC DMAR entry based on hw This avoids the need to hardcode the IOAPIC ID. Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/alderlake/acpi.c M src/soc/intel/apollolake/acpi.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/cannonlake/acpi.c M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/elkhartlake/acpi.c M src/soc/intel/jasperlake/acpi.c M src/soc/intel/meteorlake/acpi.c M src/soc/intel/skylake/acpi.c M src/soc/intel/tigerlake/acpi.c 10 files changed, 39 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/70268/1 diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index 1c820c2..b4b5201 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <console/console.h> @@ -391,8 +392,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a537b0f..b71ca64 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> #include <device/mmio.h> @@ -142,8 +143,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, defvtbar); - current += acpi_create_dmar_ds_ioapic(current, - 2, ibdf.bus, ibdf.dev, ibdf.fn); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, ibdf.bus, ibdf.dev, ibdf.fn); current += acpi_create_dmar_ds_msi_hpet(current, 0, hbdf.bus, hbdf.dev, hbdf.fn); acpi_dmar_drhd_fixup(tmp, current); diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index a9b47cc..3fe574f 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -49,8 +49,8 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) current += acpi_create_dmar_ds_msi_hpet(current, diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c index 0b898a8..4bd0063 100644 --- a/src/soc/intel/cannonlake/acpi.c +++ b/src/soc/intel/cannonlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <console/console.h> #include <device/mmio.h> @@ -222,8 +223,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, diff --git a/src/soc/intel/denverton_ns/acpi.c b/src/soc/intel/denverton_ns/acpi.c index 399bb64..af99af1 100644 --- a/src/soc/intel/denverton_ns/acpi.c +++ b/src/soc/intel/denverton_ns/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <cpu/cpu.h> #include <cpu/x86/smm.h> @@ -188,8 +189,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtbar); - current += acpi_create_dmar_ds_ioapic(current, - 2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0); current += acpi_create_dmar_ds_msi_hpet(current, 0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, 0); diff --git a/src/soc/intel/elkhartlake/acpi.c b/src/soc/intel/elkhartlake/acpi.c index 091b785..6deee1b 100644 --- a/src/soc/intel/elkhartlake/acpi.c +++ b/src/soc/intel/elkhartlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> #include <console/console.h> #include <device/device.h> @@ -191,8 +192,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 369eb02..f00ff7a 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> @@ -202,8 +203,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, diff --git a/src/soc/intel/meteorlake/acpi.c b/src/soc/intel/meteorlake/acpi.c index 54de566..93cb992 100644 --- a/src/soc/intel/meteorlake/acpi.c +++ b/src/soc/intel/meteorlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <console/console.h> @@ -191,8 +192,8 @@ tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE_ADDRESS); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 5824630..6a56071 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -208,7 +208,7 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, V_P2SB_IBDF_BUS, + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, V_P2SB_IBDF_BUS, V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_HBDF_BUS, diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index 573dc5f..305ba1b 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <acpi/acpi_gnvs.h> #include <acpi/acpigen.h> +#include <arch/ioapic.h> #include <device/mmio.h> #include <arch/smp/mpspec.h> #include <console/console.h> @@ -217,8 +218,8 @@ current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, - 2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV, V_P2SB_CFG_IBDF_FUNC); current += acpi_create_dmar_ds_msi_hpet(current, 0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV, -- To view, visit https://review.coreboot.org/c/coreboot/+/70268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0965b511e71c58f1c31433bc54595a5fabb1c206 Gerrit-Change-Number: 70268 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw
by Arthur Heymans (Code Review) 02 Dec '22

02 Dec '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70267 ) Change subject: acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw ...................................................................... acpi/acpi.c: Add a method to generate IOAPIC DRAM entries from hw This reads back the ioapic id from hardware. Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/include/acpi/acpi.h 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/70267/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index c567299..eb41409 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -898,6 +898,14 @@ SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } +unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current, + u32 addr, u8 bus, u8 dev, u8 fn) +{ + u8 enumeration_id = get_ioapic_id((void *)(uintptr_t)addr); + return acpi_create_dmar_ds(current, + SCOPE_IOAPIC, enumeration_id, bus, dev, fn); +} + unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn) { diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index 57dbc65..f66f054 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -1432,6 +1432,8 @@ unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn); +unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current, + u32 addr, u8 bus, u8 dev, u8 fn); unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, u8 dev, u8 fn); -- To view, visit https://review.coreboot.org/c/coreboot/+/70267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I214557bbe963d1086f35f96efb1cb47950099eb3 Gerrit-Change-Number: 70267 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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