coreboot-gerrit December 2022

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[M] Change in coreboot[master]: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70114 ) Change subject: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Gerrit-Change-Number: 70114 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:39:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: src/ec/intel: Create common code for board_id implementation
by Harsha B R (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70227 ) Change subject: src/ec/intel: Create common code for board_id implementation ...................................................................... Patch Set 4: (2 comments) File src/ec/intel/board_id.c: https://review.coreboot.org/c/coreboot/+/70227/comment/c05ef9e9_1eb80a49 PS3, Line 9: BOARD_ID_INIT > Yes, I'll be expand this as part of CB:66102 Ack File src/mainboard/intel/mtlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/70227/comment/ec059316_e8c3d826 PS3, Line 12: : config BOARD_SPECIFIC_OPTIONS : def_bool y : select EC_ACPI > Correction -> CB:66101 Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/70227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Gerrit-Change-Number: 70227 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:34:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Harsha B R <harsha.b.r(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: nb/intel/pineview: Use {true,false} instead of {0,1}
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70148 ) Change subject: nb/intel/pineview: Use {true,false} instead of {0,1} ...................................................................... nb/intel/pineview: Use {true,false} instead of {0,1} "use_crt" and "use_lvds" are boolean, so use "true/false". Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70148 Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/foxconn/d41s/devicetree.cb M src/mainboard/gigabyte/ga-d510ud/devicetree.cb M src/mainboard/intel/d510mo/devicetree.cb 3 files changed, 20 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/foxconn/d41s/devicetree.cb b/src/mainboard/foxconn/d41s/devicetree.cb index 766d68f..828f5bb 100644 --- a/src/mainboard/foxconn/d41s/devicetree.cb +++ b/src/mainboard/foxconn/d41s/devicetree.cb @@ -2,8 +2,8 @@ chip northbridge/intel/pineview # Northbridge register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "use_crt" = "true" + register "use_lvds" = "false" device cpu_cluster 0 on # APIC cluster chip cpu/intel/socket_FCBGA559 # CPU diff --git a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb index 9fb5ff5..18f96c64 100644 --- a/src/mainboard/gigabyte/ga-d510ud/devicetree.cb +++ b/src/mainboard/gigabyte/ga-d510ud/devicetree.cb @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only chip northbridge/intel/pineview - register "use_crt" = "1" + register "use_crt" = "true" device cpu_cluster 0 on chip cpu/intel/socket_FCBGA559 diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 4b5449f..0464b74 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -2,8 +2,8 @@ chip northbridge/intel/pineview # Northbridge register "gfx.use_spread_spectrum_clock" = "0" - register "use_crt" = "1" - register "use_lvds" = "0" + register "use_crt" = "true" + register "use_lvds" = "false" device cpu_cluster 0 on # APIC cluster chip cpu/intel/socket_FCBGA559 # CPU -- To view, visit https://review.coreboot.org/c/coreboot/+/70148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b5b42c27351331ad40fbe92fb87390cb1284aa9 Gerrit-Change-Number: 70148 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: src/ec/intel: Create common code for board_id implementation
by Harsha B R (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D. Hello build bot (Jenkins), Martin L Roth, Subrata Banik, Rizwan Qureshi, Krishna P Bhat D, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70227 to look at the new patch set (#4). Change subject: src/ec/intel: Create common code for board_id implementation ...................................................................... src/ec/intel: Create common code for board_id implementation This patch creates initial common code structure for board_id implementation for intel rvp platforms. Board_id helps in identifying the platform with respect to CHROME_EC and INTEL_EC (Windows_EC). Changes include 1. Create initial board_id.c and board_id.h 2. Modify the Makefile to include src/ec/intel directory BUG=b:260654043 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 --- M Makefile.inc A src/ec/intel/Makefile.inc A src/ec/intel/board_id.c A src/ec/intel/board_id.h 4 files changed, 48 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/70227/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/70227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If133f6a72b8c3e1d8811a11f91e4556beb8c16e0 Gerrit-Change-Number: 70227 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Usha P <usha.p(a)intel.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/system76/adl-p: Disable SATA DevSlp
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70100 ) Change subject: mb/system76/adl-p: Disable SATA DevSlp ...................................................................... mb/system76/adl-p: Disable SATA DevSlp After changing EC detection of S0ix from CPU_C10_GATE# to SLP_S0# in system76/ec@cc3effb6a451 ("board/system76/common: use SLP_S0# pin for modern standby detection"), DevSlp blocks suspend entry. Disable it until it is fixed. Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70100 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/adl-p/devicetree.cb 1 file changed, 20 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/adl-p/devicetree.cb b/src/mainboard/system76/adl-p/devicetree.cb index 6a9f362..c7085b4 100644 --- a/src/mainboard/system76/adl-p/devicetree.cb +++ b/src/mainboard/system76/adl-p/devicetree.cb @@ -73,7 +73,8 @@ device ref sata on register "sata_salp_support" = "1" register "sata_ports_enable[1]" = "1" # SSD1 - register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + # FIXME: DevSlp breaks S0ix + #register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) end device ref pch_espi on register "gen1_dec" = "0x00040069" # EC PM channel -- To view, visit https://review.coreboot.org/c/coreboot/+/70100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I586245ebf9f9d5ad08f6745a450411f194a661da Gerrit-Change-Number: 70100 Gerrit-PatchSet: 2 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/system76/adl-p: Add Galago Pro 6 as a variant
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69211 ) Change subject: mb/system76/adl-p: Add Galago Pro 6 as a variant ...................................................................... mb/system76/adl-p: Add Galago Pro 6 as a variant The Galago Pro 6 (galp6) is an Alder Lake-P board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - All USB ports - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.1 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.0.6 - Internal flashing with flashrom v1.2-1087-gde016a17 Not working: - Detection of devices in TBT slot on boot Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69211 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/system76/galp6.md M src/mainboard/system76/adl-p/Kconfig M src/mainboard/system76/adl-p/Kconfig.name A src/mainboard/system76/adl-p/variants/galp6/board_info.txt A src/mainboard/system76/adl-p/variants/galp6/data.vbt A src/mainboard/system76/adl-p/variants/galp6/gpio.c A src/mainboard/system76/adl-p/variants/galp6/gpio_early.c A src/mainboard/system76/adl-p/variants/galp6/hda_verb.c A src/mainboard/system76/adl-p/variants/galp6/overridetree.cb A src/mainboard/system76/adl-p/variants/galp6/romstage.c 11 files changed, 589 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 6911d5c..2e314e6 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -204,6 +204,7 @@ - [Darter Pro 8](system76/darp8.md) - [Galago Pro 4](system76/galp4.md) - [Galago Pro 5](system76/galp5.md) +- [Galago Pro 6](system76/galp6.md) - [Gazelle 15](system76/gaze15.md) - [Gazelle 16](system76/gaze16.md) - [Lemur Pro 9](system76/lemp9.md) diff --git a/Documentation/mainboard/system76/galp6.md b/Documentation/mainboard/system76/galp6.md new file mode 100644 index 0000000..e519dc3 --- /dev/null +++ b/Documentation/mainboard/system76/galp6.md @@ -0,0 +1,61 @@ +# System76 Galago Pro 6 (galp6) + +## Specs + +- CPU + - Intel Core i5-1240P + - Intel Core i7-1260P +- EC + - ITE IT5570E running [System76 EC](https://github.com/system76/ec) +- Graphics + - Intel Iris Xe Graphics + - eDP 14.1" 1920x1080@60Hz LCD (Panda LM140LF2L02) + - 1x HDMI 2.1 + - 1x DisplayPort 1.4 over USB-C +- Memory + - Up to 64GB (2x32GB) dual-channel DDR4 SO-DIMMs @ 3200 MHz +- Networking + - Gigabit Ethernet + - M.2 NVMe/CNVi WiFi/Bluetooth (Intel Wi-Fi 6 AX200/201) +- Power + - 90W (19V, 4.74A) AC barrel adapter (Chicony A16-090P1A) + - USB-C charging, compatible with 90W+ chargers + - 53.35Wh 4-cell Lithium-ion battery (NV40BAT-4-53) +- Sound + - Realtek ALC256 codec + - Internal speakers and microphone + - Combined 3.5mm headphone/microphone jack + - HDMI, USB-C DisplayPort audio +- Storage + - M.2 PCIe NVMe Gen 4 SSD + - MicroSD card reader (OZ711LV2) +- USB + - 1x USB-C Type-C with Thunderbolt 4 + - 1x USB 3.2 (Gen 2) Type-C + - 2x USB 3.2 (Gen 1) Type-A +- Dimensions + - 32.49cm x 22.5cm x 1.82cm, 1.45kg + +## Flashing coreboot + +```eval_rst ++---------------------+---------------------+ +| Type | Value | ++=====================+=====================+ +| Socketed flash | no | ++---------------------+---------------------+ +| Vendor | Macronix | ++---------------------+---------------------+ +| Model | MX25L25673G | ++---------------------+---------------------+ +| Size | 32 MiB | ++---------------------+---------------------+ +| Package | WSON-8 | ++---------------------+---------------------+ +| Internal flashing | yes | ++---------------------+---------------------+ +| External flashing | yes | ++---------------------+---------------------+ +``` + +The flash chip (U43) is left of the wireless card. diff --git a/src/mainboard/system76/adl-p/Kconfig b/src/mainboard/system76/adl-p/Kconfig index e9ac901..80c42a8 100644 --- a/src/mainboard/system76/adl-p/Kconfig +++ b/src/mainboard/system76/adl-p/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_DARP8 +if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_GALP6 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -28,18 +28,22 @@ config VARIANT_DIR default "darp8" if BOARD_SYSTEM76_DARP8 + default "galp6" if BOARD_SYSTEM76_GALP6 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config MAINBOARD_PART_NUMBER default "darp8" if BOARD_SYSTEM76_DARP8 + default "galp6" if BOARD_SYSTEM76_GALP6 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Darter Pro" if BOARD_SYSTEM76_DARP8 + default "Galago Pro" if BOARD_SYSTEM76_GALP6 config MAINBOARD_VERSION default "darp8" if BOARD_SYSTEM76_DARP8 + default "galp6" if BOARD_SYSTEM76_GALP6 config CBFS_SIZE default 0xA00000 diff --git a/src/mainboard/system76/adl-p/Kconfig.name b/src/mainboard/system76/adl-p/Kconfig.name index 9533451..5e3aee3 100644 --- a/src/mainboard/system76/adl-p/Kconfig.name +++ b/src/mainboard/system76/adl-p/Kconfig.name @@ -1,2 +1,5 @@ config BOARD_SYSTEM76_DARP8 bool "darp8" + +config BOARD_SYSTEM76_GALP6 + bool "galp6" diff --git a/src/mainboard/system76/adl-p/variants/galp6/board_info.txt b/src/mainboard/system76/adl-p/variants/galp6/board_info.txt new file mode 100644 index 0000000..d7ee3f4 --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/board_info.txt @@ -0,0 +1,2 @@ +Board name: galp6 +Release year: 2022 diff --git a/src/mainboard/system76/adl-p/variants/galp6/data.vbt b/src/mainboard/system76/adl-p/variants/galp6/data.vbt new file mode 100644 index 0000000..d58825f --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/data.vbt Binary files differ diff --git a/src/mainboard/system76/adl-p/variants/galp6/gpio.c b/src/mainboard/system76/adl-p/variants/galp6/gpio.c new file mode 100644 index 0000000..b73f06b --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/gpio.c @@ -0,0 +1,227 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW# + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), // LAN_WAKEUP# + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN# + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A# + PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD7_REST + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), // SLP_WLAN# + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5# + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), // LAN_DISABLE# + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC# + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0# + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET_N + PAD_NC(GPP_A11, NONE), + PAD_CFG_GPI(GPP_A12, NONE, DEEP), // SATAGP1 + PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN + // GPP_A14 (DGPU_PWR_EN) configured in bootblock + PAD_NC(GPP_A15, NONE), // USB_OC2# + PAD_NC(GPP_A16, NONE), // USB_OC3# + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), // TP_ATTN# + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), // HDMI_HPD + PAD_CFG_GPI(GPP_A19, NONE, DEEP), // DGPU_PWRGD_R + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_CFG_GPO(GPP_A22, 1, PLTRST), // GPIO_LAN_EN + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1 + // GPP_B2 (DGPU_RST#_PCH) configured in bootblock + PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI# + PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI# + PAD_NC(GPP_B5, NONE), // I2C2_SDA (Pantone) + PAD_NC(GPP_B6, NONE), // I2C2_SCL (Pantone) + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + // GPP_B9 missing + // GPP_B10 missing + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBTA-PCH_I2C_INT + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST# + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // PCH_SPKR + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), // NO REBOOT strap + // GPP_B19 missing + // GPP_B20 missing + // GPP_B21 missing + // GPP_B22 missing + PAD_NC(GPP_B23, NONE), // CPUNSSC CLOCK FREQ strap + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA + PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS CONFIDENTIALITY strap + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA + PAD_CFG_GPO(GPP_C5, 1, PLTRST), // ESPI OR EC LESS strap + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT-PCH_I2C_SCL + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT-PCH_I2C_SDA + // GPP_C8 missing + // GPP_C9 missing + // GPP_C10 missing + // GPP_C11 missing + // GPP_C12 missing + // GPP_C13 missing + // GPP_C14 missing + // GPP_C15 missing + // GPP_C16 missing + // GPP_C17 missing + // GPP_C18 missing + // GPP_C19 missing + // GPP_C20 missing + // GPP_C21 missing + // GPP_C22 missing + // GPP_C23 missing + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON + PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST# + PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + // GPP_D5 (SSD1_CLKREQ#) programmed by FSP + PAD_NC(GPP_D6, NONE), + // GPP_D7 (WLAN_CLKREQ#) programmed by FSP + // GPP_D8 (PEG_CLKREQ#) programmed by FSP + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), // TBT LSX #2 PINS VCCIO CONFIGURATION strap + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), // TBT LSX #3 PINS VCCIO CONFIGURATION strap + PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP# + PAD_CFG_GPO(GPP_D14, 1, PLTRST), // SSD1_PWR_EN# + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE# + _PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ# + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPO(GPP_E3, 1, DEEP), // PCH_WLAN_EN + PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TBT_FORCE_PWR + PAD_NC(GPP_E5, NONE), // DEVSLP1 + PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap + PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI# + PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM# + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0# + PAD_NC(GPP_E10, NONE), // strap + PAD_NC(GPP_E11, NONE), // strap + PAD_NC(GPP_E12, NONE), + PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID4 + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5 + // GPP_E18 (TBT_LSX0_TXD) configured by FSP + // GPP_E19 (TBT_LSX0_RXD) configured by FSP + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), // TBT LSX #1 PINS VCCIO CONFIGURATION strap + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST# + // GPP_F5 (CNVI_CLKREQ) programmed by FSP + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING + PAD_CFG_GPO(GPP_F7, 1, DEEP), // LAN_PLT_RST# + // GPP_F8 missing + PAD_NC(GPP_F9, NONE), + PAD_CFG_GPO(GPP_F10, 1, DEEP), // GPIO_CARD_PLT_RST# + PAD_CFG_GPI(GPP_F11, NONE, DEEP), // BOARD_ID3 + PAD_CFG_GPI(GPP_F12, NONE, PLTRST), // GPIO4_GC6_NVVDD_EN_R + PAD_CFG_GPI(GPP_F13, NONE, PLTRST), // GC6_FB_EN_PCH + PAD_CFG_GPI(GPP_F14, NONE, DEEP), // BOARD_ID1 + PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID2 + PAD_CFG_GPO(GPP_F16, 1, DEEP), // GPU_EVENT# + PAD_NC(GPP_F17, NONE), // GPIO_CARD_PWR + PAD_CFG_GPO(GPP_F18, 0, DEEP), // dGPU_OVRM + // GPP_F19 (LAN_CLKREQ#) programmed by FSP + PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M2_SSD1_RST# + PAD_NC(GPP_F21, NONE), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_NC(GPP_H0, NONE), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // T_SDA (Touchpad) + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // T_SCL (Touchpad) + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (TBT) + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (TBT) + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), // CNVI_MFUART2_TXD + // GPP_H10 (UART2_RXD) configured in bootblock + // GPP_H11 (UART2_TXD) configured in bootblock + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + // GPP_H14 missing + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), // HDMI_CTRLCLK + // GPP_H16 missing + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), // HDMI_CTRLDATA + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE# + PAD_NC(GPP_H19, NONE), + PAD_CFG_GPI(GPP_H20, NONE, DEEP), // PM_CLKRUN# + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + // GPP_H23 (CARD_CLKREQ#) programmed by FSP + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0 + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // AZ_RST#_R + PAD_NC(GPP_R5, NONE), + PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPC_DMIC_CLK + PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPC_DMIC_DATA + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c b/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c new file mode 100644 index 0000000..66577bd --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART2_RXD (actually UART0) + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART2_TXD (actually UART0) +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c new file mode 100644 index 0000000..ff2dc8e --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15584041, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584041), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb new file mode 100644 index 0000000..fc93fdc --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/overridetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/alderlake + register "power_limits_config[ADL_P_282_482_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 60, + .tdp_pl4 = 90, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x4041 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref sata off end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST# + register "srcclk_pin" = "2" # WLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, + }" + end + device ref pcie_rp10 on + # PCIe RP#10 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST# + register "srcclk_pin" = "6" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/system76/adl-p/variants/galp6/romstage.c b/src/mainboard/system76/adl-p/variants/galp6/romstage.c new file mode 100644 index 0000000..3d6a5fb --- /dev/null +++ b/src/mainboard/system76/adl-p/variants/galp6/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/69211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8940fb3777d7f18393ef50baec32f9445b375648 Gerrit-Change-Number: 69211 Gerrit-PatchSet: 4 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[master]: mb/system76/cml-u: Convert lemp9 to a variant
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/64528 ) Change subject: mb/system76/cml-u: Convert lemp9 to a variant ...................................................................... mb/system76/cml-u: Convert lemp9 to a variant Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae Signed-off-by: Tim Crawford <tcrawford(a)system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/64528 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jeremy Soller <jeremy(a)system76.com> --- M src/mainboard/system76/cml-u/Kconfig M src/mainboard/system76/cml-u/Kconfig.name M src/mainboard/system76/cml-u/Makefile.inc M src/mainboard/system76/cml-u/devicetree.cb R src/mainboard/system76/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex R src/mainboard/system76/cml-u/variants/darp6/gpio.c M src/mainboard/system76/cml-u/variants/darp6/overridetree.cb R src/mainboard/system76/cml-u/variants/darp6/romstage.c C src/mainboard/system76/cml-u/variants/galp4/gpio.c M src/mainboard/system76/cml-u/variants/galp4/overridetree.cb C src/mainboard/system76/cml-u/variants/galp4/romstage.c A src/mainboard/system76/cml-u/variants/lemp9/board_info.txt R src/mainboard/system76/cml-u/variants/lemp9/data.vbt R src/mainboard/system76/cml-u/variants/lemp9/gpio.c R src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c A src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb C src/mainboard/system76/cml-u/variants/lemp9/romstage.c D src/mainboard/system76/lemp9/Kconfig D src/mainboard/system76/lemp9/Kconfig.name D src/mainboard/system76/lemp9/Makefile.inc D src/mainboard/system76/lemp9/acpi/gpe.asl D src/mainboard/system76/lemp9/acpi/mainboard.asl D src/mainboard/system76/lemp9/acpi/sleep.asl D src/mainboard/system76/lemp9/board_info.txt D src/mainboard/system76/lemp9/bootblock.c D src/mainboard/system76/lemp9/cmos.default D src/mainboard/system76/lemp9/cmos.layout D src/mainboard/system76/lemp9/devicetree.cb D src/mainboard/system76/lemp9/dsdt.asl D src/mainboard/system76/lemp9/ramstage.c D src/mainboard/system76/lemp9/romstage.c 31 files changed, 236 insertions(+), 558 deletions(-) Approvals: build bot (Jenkins): Verified Jeremy Soller: Looks good to me, approved diff --git a/src/mainboard/system76/cml-u/Kconfig b/src/mainboard/system76/cml-u/Kconfig index 1c1ebbe..992f8dc 100644 --- a/src/mainboard/system76/cml-u/Kconfig +++ b/src/mainboard/system76/cml-u/Kconfig @@ -1,4 +1,4 @@ -if BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_DARP6 +if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 || BOARD_SYSTEM76_LEMP9 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -10,13 +10,15 @@ select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE + select HAVE_SPD_IN_CBFS if BOARD_SYSTEM76_LEMP9 select INTEL_GMA_HAVE_VBT select INTEL_LPSS_UART_FOR_CONSOLE select MEMORY_MAPPED_TPM select MAINBOARD_HAS_TPM2 select NO_UART_ON_SUPERIO - select PCIEXP_HOTPLUG - select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G # Fix running out of MTRRs + select PCIEXP_HOTPLUG if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 + # Fix running out of MTRRs + select PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G if BOARD_SYSTEM76_DARP6 || BOARD_SYSTEM76_GALP4 select SOC_INTEL_COMETLAKE_1 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SPD_READ_BY_WORD @@ -29,6 +31,7 @@ config VARIANT_DIR default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -36,16 +39,20 @@ config MAINBOARD_PART_NUMBER default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config MAINBOARD_SMBIOS_PRODUCT_NAME default "Galago Pro" if BOARD_SYSTEM76_GALP4 default "Darter Pro" if BOARD_SYSTEM76_DARP6 + default "Lemur Pro" if BOARD_SYSTEM76_LEMP9 config MAINBOARD_VERSION default "galp4" if BOARD_SYSTEM76_GALP4 default "darp6" if BOARD_SYSTEM76_DARP6 + default "lemp9" if BOARD_SYSTEM76_LEMP9 config CBFS_SIZE + default 0xc00000 if BOARD_SYSTEM76_LEMP9 default 0xA00000 config CONSOLE_POST diff --git a/src/mainboard/system76/cml-u/Kconfig.name b/src/mainboard/system76/cml-u/Kconfig.name index 30478ca..258ee08 100644 --- a/src/mainboard/system76/cml-u/Kconfig.name +++ b/src/mainboard/system76/cml-u/Kconfig.name @@ -3,3 +3,6 @@ config BOARD_SYSTEM76_DARP6 bool "darp6" + +config BOARD_SYSTEM76_LEMP9 + bool "lemp9" diff --git a/src/mainboard/system76/cml-u/Makefile.inc b/src/mainboard/system76/cml-u/Makefile.inc index d749e41..5276308 100644 --- a/src/mainboard/system76/cml-u/Makefile.inc +++ b/src/mainboard/system76/cml-u/Makefile.inc @@ -4,5 +4,7 @@ bootblock-y += gpio_early.c ramstage-y += ramstage.c -ramstage-y += gpio.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c + +SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/system76/cml-u/devicetree.cb b/src/mainboard/system76/cml-u/devicetree.cb index da86024..86e7aa4 100644 --- a/src/mainboard/system76/cml-u/devicetree.cb +++ b/src/mainboard/system76/cml-u/devicetree.cb @@ -70,31 +70,14 @@ device pci 12.5 off end # UFS SCS device pci 12.6 off end # GSPI #2 device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE - register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 - register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT - register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT - end device pci 14.1 off end # USB xDCI (OTG) device pci 14.3 on # CNVi wifi chip drivers/wifi/generic - register "wake" = "PME_B0_EN_BIT" + register "wake" = "GPE0_PME_B0" device generic 0 on end end end device pci 14.5 off end # SDCard - device pci 15.0 on end # I2C #0 device pci 15.1 off end # I2C #1 device pci 15.2 off end # I2C #2 device pci 15.3 off end # I2C #3 @@ -104,52 +87,23 @@ device pci 16.3 off end # Management Engine KT Redirection device pci 16.4 off end # Management Engine Interface 3 device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" - end device pci 19.0 off end # I2C #4 device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 off end # eMMC - device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.0 off end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 - # PCI Express Root port #5 x4, Clock 4 (TBT) - register "PcieRpEnable[4]" = "1" - register "PcieRpLtrEnable[4]" = "1" - register "PcieRpHotPlug[4]" = "1" - register "PcieClkSrcUsage[4]" = "4" - register "PcieClkSrcClkReq[4]" = "4" - end + device pci 1c.4 off end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 - # PCI Express Root port #9 x1, Clock 3 (LAN) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[3]" = "8" - register "PcieClkSrcClkReq[3]" = "3" - end - device pci 1d.1 on # PCI Express Port 10 - # PCI Express Root port #10 x1, Clock 2 (WLAN) - register "PcieRpEnable[9]" = "1" - register "PcieRpLtrEnable[9]" = "0" - register "PcieClkSrcUsage[2]" = "9" - register "PcieClkSrcClkReq[2]" = "2" - end + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - # PCI Express Root port #13 x4, Clock 5 (NVMe) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[5]" = "12" - register "PcieClkSrcClkReq[5]" = "5" - end + device pci 1d.4 off end # PCI Express Port 13 device pci 1d.5 off end # PCI Express Port 14 device pci 1d.6 off end # PCI Express Port 15 device pci 1d.7 off end # PCI Express Port 16 @@ -169,8 +123,6 @@ device pci 1f.2 hidden end # Power Management Controller device pci 1f.3 on # Intel HDA register "PchHdaAudioLinkHda" = "1" - register "PchHdaAudioLinkDmic0" = "1" - register "PchHdaAudioLinkDmic1" = "1" end device pci 1f.4 on end # SMBus device pci 1f.5 on end # PCH SPI diff --git a/src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex b/src/mainboard/system76/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex similarity index 100% rename from src/mainboard/system76/lemp9/spd/samsung-K4AAG165WA-BCTD.spd.hex rename to src/mainboard/system76/cml-u/spd/samsung-K4AAG165WA-BCTD.spd.hex diff --git a/src/mainboard/system76/cml-u/gpio.c b/src/mainboard/system76/cml-u/variants/darp6/gpio.c similarity index 99% rename from src/mainboard/system76/cml-u/gpio.c rename to src/mainboard/system76/cml-u/variants/darp6/gpio.c index 03683ae..41353a9 100644 --- a/src/mainboard/system76/cml-u/gpio.c +++ b/src/mainboard/system76/cml-u/variants/darp6/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <mainboard/gpio.h> -#include <soc/gpe.h> #include <soc/gpio.h> static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb index 631803c..a39622c 100644 --- a/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/darp6/overridetree.cb @@ -1,7 +1,24 @@ chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1404 inherit - device pci 15.0 on + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + end + device pci 15.0 on # I2C #0 chip drivers/i2c/hid register "generic.hid" = ""SYNA1202"" register "generic.desc" = ""Synaptics Touchpad"" @@ -10,6 +27,43 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end - end # I2C #0 + end + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.0 on # PCI Express Port 9 + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.1 on # PCI Express Port 10 + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1d.4 on # PCI Express Port 13 + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + end + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + end end end diff --git a/src/mainboard/system76/cml-u/romstage.c b/src/mainboard/system76/cml-u/variants/darp6/romstage.c similarity index 83% rename from src/mainboard/system76/cml-u/romstage.c rename to src/mainboard/system76/cml-u/variants/darp6/romstage.c index 1cd82c6..aae639b 100644 --- a/src/mainboard/system76/cml-u/romstage.c +++ b/src/mainboard/system76/cml-u/variants/darp6/romstage.c @@ -6,11 +6,11 @@ static const struct cnl_mb_cfg memcfg = { .spd[0] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, + .spd_spec = { .spd_smbus_address = 0xa0 }, }, .spd[2] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, + .spd_spec = { .spd_smbus_address = 0xa4 }, }, .rcomp_resistor = { 121, 81, 100 }, .rcomp_targets = { 100, 40, 20, 20, 26 }, diff --git a/src/mainboard/system76/cml-u/gpio.c b/src/mainboard/system76/cml-u/variants/galp4/gpio.c similarity index 99% copy from src/mainboard/system76/cml-u/gpio.c copy to src/mainboard/system76/cml-u/variants/galp4/gpio.c index 03683ae..41353a9 100644 --- a/src/mainboard/system76/cml-u/gpio.c +++ b/src/mainboard/system76/cml-u/variants/galp4/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <mainboard/gpio.h> -#include <soc/gpe.h> #include <soc/gpio.h> static const struct pad_config gpio_table[] = { diff --git a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb index f6c6149..f6be0eb 100644 --- a/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb +++ b/src/mainboard/system76/cml-u/variants/galp4/overridetree.cb @@ -1,8 +1,62 @@ chip soc/intel/cannonlake device domain 0 on subsystemid 0x1558 0x1403 inherit - device pci 15.0 on + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + end + device pci 15.0 on # I2C #0 # I2C HID not supported on galp4 - end # I2C #0 + end + device pci 17.0 on # SATA + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[2]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + end + device pci 1d.0 on # PCI Express Port 9 + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device pci 1d.1 on # PCI Express Port 10 + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + end + device pci 1d.4 on # PCI Express Port 13 + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + end + device pci 1f.3 on # Intel HDA + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + end end end diff --git a/src/mainboard/system76/cml-u/romstage.c b/src/mainboard/system76/cml-u/variants/galp4/romstage.c similarity index 83% copy from src/mainboard/system76/cml-u/romstage.c copy to src/mainboard/system76/cml-u/variants/galp4/romstage.c index 1cd82c6..aae639b 100644 --- a/src/mainboard/system76/cml-u/romstage.c +++ b/src/mainboard/system76/cml-u/variants/galp4/romstage.c @@ -6,11 +6,11 @@ static const struct cnl_mb_cfg memcfg = { .spd[0] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, + .spd_spec = { .spd_smbus_address = 0xa0 }, }, .spd[2] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, + .spd_spec = { .spd_smbus_address = 0xa4 }, }, .rcomp_resistor = { 121, 81, 100 }, .rcomp_targets = { 100, 40, 20, 20, 26 }, diff --git a/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt new file mode 100644 index 0000000..c547c6a --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/lemp9/board_info.txt @@ -0,0 +1,2 @@ +Board name: lemp9 +Release year: 2020 diff --git a/src/mainboard/system76/lemp9/data.vbt b/src/mainboard/system76/cml-u/variants/lemp9/data.vbt similarity index 100% rename from src/mainboard/system76/lemp9/data.vbt rename to src/mainboard/system76/cml-u/variants/lemp9/data.vbt Binary files differ diff --git a/src/mainboard/system76/lemp9/gpio.h b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c similarity index 93% rename from src/mainboard/system76/lemp9/gpio.h rename to src/mainboard/system76/cml-u/variants/lemp9/gpio.c index 59d8d06..d27acad 100644 --- a/src/mainboard/system76/lemp9/gpio.h +++ b/src/mainboard/system76/cml-u/variants/lemp9/gpio.c @@ -1,23 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - +#include <mainboard/gpio.h> #include <soc/gpio.h> -#ifndef __ACPI__ - -/* Name format: <pad name> / <net/pin name in schematics> */ - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* UART2_RXD */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* UART2_TXD */ - PAD_NC(GPP_C22, UP_20K), - PAD_NC(GPP_C23, UP_20K), -}; - -/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* ------- GPIO Group GPD ------- */ PAD_NC(GPD0, NONE), @@ -248,6 +233,7 @@ PAD_NC(GPP_H23, UP_20K), }; -#endif - -#endif +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/lemp9/hda_verb.c b/src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c similarity index 100% rename from src/mainboard/system76/lemp9/hda_verb.c rename to src/mainboard/system76/cml-u/variants/lemp9/hda_verb.c diff --git a/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb new file mode 100644 index 0000000..e85cf63 --- /dev/null +++ b/src/mainboard/system76/cml-u/variants/lemp9/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/cannonlake + device domain 0 on + subsystemid 0x1558 0x1401 inherit + + device pci 14.0 on # USB xHCI + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 + end + device pci 15.0 on # I2C #0 + chip drivers/i2c/hid + register "generic.hid" = ""ELAN040D"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + end + device pci 17.0 on # SATA + register "SataSalpSupport" = "1" + # Port 2 (J_SSD2) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + # Port 3 (J_SSD1) + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[2]" = "1" + end + device pci 1c.5 on # PCI Express Port 6 + device pci 00.0 on end # x1 Card reader + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[3]" = "5" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieRpSlotImplemented[5]" = "1" + end + device pci 1c.7 on # PCI Express Port 8 + device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[2]" = "7" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieRpSlotImplemented[7]" = "1" + chip drivers/wifi/generic + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device pci 1d.0 on # PCI Express Port 9 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device pci 1d.4 on # PCI Express Port 13 + device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieRpSlotImplemented[12]" = "1" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + end +end diff --git a/src/mainboard/system76/cml-u/romstage.c b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c similarity index 79% copy from src/mainboard/system76/cml-u/romstage.c copy to src/mainboard/system76/cml-u/variants/lemp9/romstage.c index 1cd82c6..2be3353 100644 --- a/src/mainboard/system76/cml-u/romstage.c +++ b/src/mainboard/system76/cml-u/variants/lemp9/romstage.c @@ -5,12 +5,12 @@ static const struct cnl_mb_cfg memcfg = { .spd[0] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa0}, + .read_type = READ_SPD_CBFS, + .spd_spec = { .spd_index = 0 }, }, .spd[2] = { .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, + .spd_spec = { .spd_smbus_address = 0xa4 }, }, .rcomp_resistor = { 121, 81, 100 }, .rcomp_targets = { 100, 40, 20, 20, 26 }, diff --git a/src/mainboard/system76/lemp9/Kconfig b/src/mainboard/system76/lemp9/Kconfig deleted file mode 100644 index dbc9de2..0000000 --- a/src/mainboard/system76/lemp9/Kconfig +++ /dev/null @@ -1,66 +0,0 @@ -if BOARD_SYSTEM76_LEMP9 - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOARD_ROMSIZE_KB_16384 - select DRIVERS_I2C_HID - select EC_SYSTEM76_EC - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE - select HAVE_SMI_HANDLER - select HAVE_SPD_IN_CBFS - select INTEL_GMA_HAVE_VBT - select INTEL_LPSS_UART_FOR_CONSOLE - select MEMORY_MAPPED_TPM - select MAINBOARD_HAS_TPM2 - select NO_UART_ON_SUPERIO - select SOC_INTEL_COMETLAKE_1 - select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SPD_READ_BY_WORD - select SYSTEM_TYPE_LAPTOP - select TPM_MEASURED_BOOT - select USE_LEGACY_8254_TIMER # Fix failure to boot GRUB - -config MAINBOARD_DIR - default "system76/lemp9" - -config MAINBOARD_PART_NUMBER - default "lemp9" - -config MAINBOARD_SMBIOS_PRODUCT_NAME - string - default "Lemur Pro" - -config MAINBOARD_VERSION - string - default "lemp9" - -config CBFS_SIZE - default 0xc00000 - -config CONSOLE_POST - bool - default y - -config UART_FOR_CONSOLE - int - default 2 - -config DIMM_MAX - default 2 - -config VGA_BIOS_ID - string - default "8086,9b41" - -config TPM_PIRQ - hex - default 0x10 # GPP_A7/PIRQA# - -config POST_DEVICE - bool - default n - -endif diff --git a/src/mainboard/system76/lemp9/Kconfig.name b/src/mainboard/system76/lemp9/Kconfig.name deleted file mode 100644 index 4a4ab68..0000000 --- a/src/mainboard/system76/lemp9/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SYSTEM76_LEMP9 - bool "lemp9" diff --git a/src/mainboard/system76/lemp9/Makefile.inc b/src/mainboard/system76/lemp9/Makefile.inc deleted file mode 100644 index 3d742d6..0000000 --- a/src/mainboard/system76/lemp9/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -bootblock-y += bootblock.c -ramstage-y += ramstage.c -ramstage-y += hda_verb.c -SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/system76/lemp9/acpi/gpe.asl b/src/mainboard/system76/lemp9/acpi/gpe.asl deleted file mode 100644 index c1bc04d..0000000 --- a/src/mainboard/system76/lemp9/acpi/gpe.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// GPP_D9 SCI -Method (_L29, 0, Serialized) { - Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) - If (\_SB.PCI0.LPCB.EC0.ECOK) { - If (\_SB.PCI0.LPCB.EC0.WFNO == One) { - Notify(\_SB.LID0, 0x80) - } - } -} diff --git a/src/mainboard/system76/lemp9/acpi/mainboard.asl b/src/mainboard/system76/lemp9/acpi/mainboard.asl deleted file mode 100644 index 416cc5a..0000000 --- a/src/mainboard/system76/lemp9/acpi/mainboard.asl +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#define EC_GPE_SCI 0x50 /* GPP_E16 */ -#define EC_GPE_SWI 0x29 /* GPP_D9 */ -#include <ec/system76/ec/acpi/ec.asl> - -Scope (\_SB) { - #include "sleep.asl" -} - -Scope (\_GPE) { - #include "gpe.asl" -} diff --git a/src/mainboard/system76/lemp9/acpi/sleep.asl b/src/mainboard/system76/lemp9/acpi/sleep.asl deleted file mode 100644 index 48c50e0..0000000 --- a/src/mainboard/system76/lemp9/acpi/sleep.asl +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Method called from _PTS prior to enter sleep state */ -Method (MPTS, 1) { - \_SB.PCI0.LPCB.EC0.PTS (Arg0) -} - -/* Method called from _WAK prior to wakeup */ -Method (MWAK, 1) { - \_SB.PCI0.LPCB.EC0.WAK (Arg0) -} diff --git a/src/mainboard/system76/lemp9/board_info.txt b/src/mainboard/system76/lemp9/board_info.txt deleted file mode 100644 index f6784ef..0000000 --- a/src/mainboard/system76/lemp9/board_info.txt +++ /dev/null @@ -1,8 +0,0 @@ -Vendor name: System76 -Board name: lemp9 -Category: laptop -Release year: 2020 -ROM package: SOIC-8 -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/system76/lemp9/bootblock.c b/src/mainboard/system76/lemp9/bootblock.c deleted file mode 100644 index fd6070c..0000000 --- a/src/mainboard/system76/lemp9/bootblock.c +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> -#include <gpio.h> -#include "gpio.h" - -void bootblock_mainboard_early_init(void) -{ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/system76/lemp9/cmos.default b/src/mainboard/system76/lemp9/cmos.default deleted file mode 100644 index 0d37675..0000000 --- a/src/mainboard/system76/lemp9/cmos.default +++ /dev/null @@ -1,3 +0,0 @@ -boot_option=Fallback -debug_level=Debug -me_state=Disable diff --git a/src/mainboard/system76/lemp9/cmos.layout b/src/mainboard/system76/lemp9/cmos.layout deleted file mode 100644 index a53c3f4..0000000 --- a/src/mainboard/system76/lemp9/cmos.layout +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -entries - -0 384 r 0 reserved_memory - -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# RTC_CLK_ALTCENTURY -400 8 r 0 century - -412 4 e 6 debug_level -416 1 e 2 me_state -417 3 h 0 me_state_counter -984 16 h 0 check_sum - -enumerations - -2 0 Enable -2 1 Disable - -4 0 Fallback -4 1 Normal - -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 408 983 984 diff --git a/src/mainboard/system76/lemp9/devicetree.cb b/src/mainboard/system76/lemp9/devicetree.cb deleted file mode 100644 index 77ba265..0000000 --- a/src/mainboard/system76/lemp9/devicetree.cb +++ /dev/null @@ -1,201 +0,0 @@ -chip soc/intel/cannonlake - register "common_soc_config" = "{ - /* Touchpad */ - .i2c[0] = { - .speed = I2C_SPEED_FAST, - .rise_time_ns = 80, - .fall_time_ns = 110, - }, - }" - -# CPU (soc/intel/cannonlake/cpu.c) - # Power limit - register "power_limits_config" = "{ - .tdp_pl1_override = 20, - .tdp_pl2_override = 30, - }" - - # Enable Enhanced Intel SpeedStep - register "eist_enable" = "1" - -# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) - register "SaGv" = "SaGv_Enabled" - #register "enable_c6dram" = "1" - -# FSP Silicon (soc/intel/cannonlake/fsp_params.c) - # Serial I/O - register "SerialIoDevMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, // Touchpad - [PchSerialIoIndexUART2] = PchSerialIoSkipInit, // LPSS UART - }" - - # Misc - register "AcousticNoiseMitigation" = "1" - #register "dmipwroptimize" = "1" - #register "satapwroptimize" = "1" - - # Power - register "PchPmSlpS3MinAssert" = "3" # 50ms - register "PchPmSlpS4MinAssert" = "1" # 1s - register "PchPmSlpSusMinAssert" = "2" # 500ms - register "PchPmSlpAMinAssert" = "4" # 2s - - # Thermal - register "tcc_offset" = "12" - -# PM Util (soc/intel/cannonlake/pmutil.c) - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) - register "gpe0_dw0" = "PMC_GPP_C" - register "gpe0_dw1" = "PMC_GPP_D" - register "gpe0_dw2" = "PMC_GPP_E" - -# Actual device tree - device cpu_cluster 0 on - device lapic 0 on end - end - - device domain 0 on - subsystemid 0x1558 0x1401 inherit - device pci 00.0 on end # Host Bridge - device pci 02.0 on # Integrated Graphics Device - register "gfx" = "GMA_DEFAULT_PANEL(0)" - end - device pci 04.0 on # SA Thermal device - register "Device4Enable" = "1" - end - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # Integrated Sensor Hub - device pci 14.0 on # USB xHCI - # USB2 - register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 3 - register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth - # USB3 - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C port 2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 3 - end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi wifi - device pci 14.5 off end # SDCard - device pci 15.0 on - chip drivers/i2c/hid - register "generic.hid" = ""ELAN040D"" - register "generic.desc" = ""ELAN Touchpad"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.detect" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 15 on end - end - end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA - register "SataSalpSupport" = "1" - # Port 2 (J_SSD2) - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" - # Port 3 (J_SSD1) - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[2]" = "1" - end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 on # PCI Express Port 6 - device pci 00.0 on end # x1 Card reader - register "PcieRpEnable[5]" = "1" - register "PcieRpLtrEnable[5]" = "1" - register "PcieClkSrcUsage[3]" = "5" - register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[5]" = "1" - end - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 on # PCI Express Port 8 - device pci 00.0 on end # x1 M.2/E 2230 (J_WLAN1) - register "PcieRpEnable[7]" = "1" - register "PcieRpLtrEnable[7]" = "1" - register "PcieClkSrcUsage[2]" = "7" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieRpSlotImplemented[7]" = "1" - chip drivers/wifi/generic - device pci 00.0 on end - end - smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" - end - device pci 1d.0 on # PCI Express Port 9 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD2) - register "PcieRpEnable[8]" = "1" - register "PcieRpLtrEnable[8]" = "1" - register "PcieClkSrcUsage[4]" = "8" - register "PcieClkSrcClkReq[4]" = "4" - register "PcieRpSlotImplemented[8]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" - end - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 on # PCI Express Port 13 - device pci 00.0 on end # x4 M.2/M 2280 (J_SSD1) - register "PcieRpEnable[12]" = "1" - register "PcieRpLtrEnable[12]" = "1" - register "PcieClkSrcUsage[5]" = "12" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieRpSlotImplemented[12]" = "1" - smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" - end - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface - # LPC configuration from lspci -s 1f.0 -xxx - # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) - register "gen1_dec" = "0x00040069" - # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) - register "gen2_dec" = "0x00fc0E01" - # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) - register "gen3_dec" = "0x00fc0F01" - chip drivers/pc80/tpm # TPM - device pnp 0c31.0 on end - end - end - device pci 1f.1 off end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on # Intel HDA - register "PchHdaAudioLinkHda" = "1" - end - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/system76/lemp9/dsdt.asl b/src/mainboard/system76/lemp9/dsdt.asl deleted file mode 100644 index b633254..0000000 --- a/src/mainboard/system76/lemp9/dsdt.asl +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <acpi/acpi.h> -DefinitionBlock( - "dsdt.aml", - "DSDT", - ACPI_DSDT_REV_2, - OEM_ID, - ACPI_TABLE_CREATOR, - 0x20110725 -) -{ - #include <acpi/dsdt_top.asl> - #include <soc/intel/common/block/acpi/acpi/platform.asl> - #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> - #include <cpu/intel/common/acpi/cpu.asl> - - Device (\_SB.PCI0) - { - #include <soc/intel/common/block/acpi/acpi/northbridge.asl> - #include <soc/intel/cannonlake/acpi/southbridge.asl> - } - - #include <southbridge/intel/common/acpi/sleepstates.asl> - - Scope (\_SB.PCI0.LPCB) - { - #include <drivers/pc80/pc/ps2_controller.asl> - } - - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/system76/lemp9/ramstage.c b/src/mainboard/system76/lemp9/ramstage.c deleted file mode 100644 index a5ada97..0000000 --- a/src/mainboard/system76/lemp9/ramstage.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/ramstage.h> -#include "gpio.h" -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} - -void mainboard_silicon_init_params(FSPS_UPD *supd) -{ - /* Configure pads prior to SiliconInit() in case there's any - * dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} diff --git a/src/mainboard/system76/lemp9/romstage.c b/src/mainboard/system76/lemp9/romstage.c deleted file mode 100644 index 3b9c896..0000000 --- a/src/mainboard/system76/lemp9/romstage.c +++ /dev/null @@ -1,51 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/cnl_memcfg_init.h> -#include <soc/romstage.h> - -static const struct cnl_mb_cfg memcfg = { - /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ - .spd[0] = { - .read_type = READ_SPD_CBFS, - .spd_spec = {.spd_index = 0}, - }, - .spd[1] = {.read_type = NOT_EXISTING}, - .spd[2] = { - .read_type = READ_SMBUS, - .spd_spec = {.spd_smbus_address = 0xa4}, - }, - .spd[3] = {.read_type = NOT_EXISTING}, - - /* - * Rcomp resistor values. These values represent the resistance in - * ohms of the three rcomp resistors attached to the DDR_COMP_0, - * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. - */ - .rcomp_resistor = { 121, 81, 100 }, - - /* Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, - - /* - * Indicates whether memory is interleaved. - * Set to 1 for an interleaved design, - * set to 0 for non-interleaved design. - */ - .dq_pins_interleaved = 1, - - /* - * VREF_CA configuration. - * Set to 0 VREF_CA goes to both CH_A and CH_B, - * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, - * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. - */ - .vref_ca_config = 2, - - /* Early Command Training */ - .ect = 0, -}; - -void mainboard_memory_init_params(FSPM_UPD *memupd) -{ - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/64528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13777cf6f663ca8c52a059a60cfcdfe6ecc5b9ae Gerrit-Change-Number: 64528 Gerrit-PatchSet: 5 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/herobrine: Update FMD file for multiple ROM sizes
by Felix Held (Code Review) 02 Dec '22

02 Dec '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69939 ) Change subject: mb/google/herobrine: Update FMD file for multiple ROM sizes ...................................................................... mb/google/herobrine: Update FMD file for multiple ROM sizes The Piglin & Hoglin boards were built with a couple of different sizes of ROM chips. Despite this, the desire was to use just a single FMD file. The different sizes are already accounted for in Kconfig, so add the Kconfig size here to be used. Signed-off-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69939 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Shelley Chen <shchen(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/herobrine/chromeos.fmd 1 file changed, 25 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Shelley Chen: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/herobrine/chromeos.fmd b/src/mainboard/google/herobrine/chromeos.fmd index cb56d73..b7633a4 100644 --- a/src/mainboard/google/herobrine/chromeos.fmd +++ b/src/mainboard/google/herobrine/chromeos.fmd @@ -1,7 +1,12 @@ ## SPDX-License-Identifier: GPL-2.0-only # TODO: update for Herobrine + +#if CONFIG_BOARD_GOOGLE_PIGLIN || CONFIG_BOARD_GOOGLE_HOGLIN +FLASH@0x0 CONFIG_ROM_SIZE { +#else FLASH@0x0 8M { +#endif WP_RO 4M { RO_SECTION 0x3c4000 { BOOTBLOCK 96K -- To view, visit https://review.coreboot.org/c/coreboot/+/69939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia75725b0c4d61e832c94160fa4cd455e89c60274 Gerrit-Change-Number: 69939 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-CC: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-CC: mturney mturney <mturney(a)codeaurora.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate
by Eric Lai (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Michał Żygowski, Elyes Haouas, Felix Held, Piotr Król. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70255 ) Change subject: superio/nuvoton/nct5104d/chip.h: Use 'bool' when appropriate ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: I think it's proper to keep 1/0 by the comment, it's bit wise register value. IRQ type selection (1:level,0:edge) -- To view, visit https://review.coreboot.org/c/coreboot/+/70255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idb321302bc82eb1b73bc1e732b82b9f726d2f363 Gerrit-Change-Number: 70255 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:26:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots
by Angel Pons (Code Review) 02 Dec '22

02 Dec '22

Attention is currently required from: Anjaneya "Reddy" Chagam, Jonathan Zhang, Johnny Lin, Christian Walter, Arthur Heymans, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64036 ) Change subject: soc/intel/xeon_sp/cpx: Allow creating meminfo for empty DIMM slots ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/cpx/romstage.c: https://review.coreboot.org/c/coreboot/+/64036/comment/d027644c_6a647f90 PS1, Line 153: DIMMs > Yes I think printing both would be better. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d9c41dd7d981842ca6f0294d9e6b0fedc0c98e4 Gerrit-Change-Number: 64036 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 02 Dec 2022 14:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit December 2022